design_engineer
Newbie level 6
My SCANEN signal has a fanout of over 11000.
I have a set_false_path -from SCANEN in my constraints.
When I run optDesign in Encounter, it is not building a buffer tree on the SCANEN net. Is the false path causing the tool to ignore the fanout violation? But if I take out the false path, then I will fail timing on the scan signal. This will make the tool work unnecessarily to meet timing on test paths I dont really care about.
How do I deal with this?
I have a set_false_path -from SCANEN in my constraints.
When I run optDesign in Encounter, it is not building a buffer tree on the SCANEN net. Is the false path causing the tool to ignore the fanout violation? But if I take out the false path, then I will fail timing on the scan signal. This will make the tool work unnecessarily to meet timing on test paths I dont really care about.
How do I deal with this?