encounter load timing library

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SophieDupuis

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Hi everybody,

I have a placed and routed circuit in .def format and I would like to analyze its delay and power consumption.

I have managed to open the .def with loadDefFile (before that I have used loadLefFile for the techno and the library files).
But when I try to analyze delay or power consumption, I have the error message "Timing Library is not loaded yet".
It seems logical that the .lib file is needed but I don't know how to load it.

Thank you.
 

for the latest version of Encounter, the MMMC is by default:
then you need this kind of commands:
Code: 
set init_verilog  "toto.v"
set init_top_cell <top_name>
set init_lef_file <list of lef files>
set init_pwr_net "vddd"
set init_gnd_net "gndd"
set init_mmmc_file ./SCRIPTS/mmmc.tcl 
init_design

# load floorplan
defIn toto.def
init_design

with mmc.tcl example:

Code: 
create_library_set -name LIBSET_WC	-timing "$lib_list_wc"
create_library_set -name LIBSET_BC	-timing "$lib_list_bc"

create_rc_corner -name rc_best \
	-cap_table toto.capTbl \
	-preRoute_res 1 \
	-postRoute_res 1 \
	-preRoute_cap 1 \
	-postRoute_cap 1 \
	-postRoute_xcap 1 \
	-postRoute_clkres 0 \
	-postRoute_clkcap 0 \

create_rc_corner -name rc_worst \
	-cap_table toto.capTbl \
	-preRoute_res 1 \
	-postRoute_res 1 \
	-preRoute_cap 1 \
	-postRoute_cap 1 \
	-postRoute_xcap 1 \
	-postRoute_clkres 0 \
	-postRoute_clkcap 0 \

create_delay_corner -name WC_dc -library_set LIBSET_WC  -opcond_library "wc"  -rc_corner rc_worst

create_delay_corner -name BC_dc -library_set LIBSET_BC  -opcond_library "bc"  -rc_corner rc_best

create_constraint_mode -name CM -sdc_file toto.sdc
   
create_analysis_view -name AV_WC_RCWORST -constraint_mode CM -delay_corner WC_dc
create_analysis_view -name AV_BC_RCBEST   -constraint_mode CM -delay_corner BC_dc

set_analysis_view -setup "AV_WC_RCWORST" -hold "AV_WC_RCWORST AV_BC_RCBEST"
 
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