Encounter Library Characterizer Feedthrough Problem

Greetings,

I have been wrestling with ELC for some time and can't seem to solve this one particular problem. The tool does not recognize my gates properly and can't establish inputs and outputs, instead it is counting them as feedthrough pins and connects them to the ground. Following is the error I get:

--------------------
D0000: : POWER
--------------------
=> 1 vectors generated
Writing : foo.ipdb/INV.design/simulate/spec
Writing : foo.ipdb/INV.design/simulate/subckt
[WARNING(db_gsim)]alone net : A is found. => [reset to ground]
[WARNING(db_gsim)]Please check whether supply nodes are marked global in the net list, if not specify them with .global statements
[WARNING(db_gsim)]alone net : Y is found. => [reset to ground]
[WARNING(db_gsim)]Please check whether supply nodes are marked global in the net list, if not specify them with .global statements
[WARNING(db_gsim)]alone net : VDD is found. => [reset to ground]
[WARNING(db_gsim)]Please check whether supply nodes are marked global in the net list, if not specify them with .global statements
[WARNING(db_gsim)]alone net : GND is found. => [reset to ground]
[WARNING(db_gsim)]Please check whether supply nodes are marked global in the net list, if not specify them with .global statements
Writing : foo.ipdb/INV.design/boundary/port
Writing : foo.ipdb/INV.design/body/type

And after that this is how the tool sees the gate:

==============================
DESIGN : INV
==============================
DESIGN ( INV );
// =================
// PORT DEFINITION
// =================
SUPPLY0 GND ( GND );
SUPPLY1 VDD ( VDD );
FEEDTHRU A ( A );
FEEDTHRU Y ( Y );
// ===========
// INSTANCES
// ===========
END_OF_DESIGN;

- feed-through ( A ) is found
- feed-through ( Y ) is found


Since it says check the global nets, I added every possible combination of global net definitions in the subcircuit file. I have been dwelling on this for a long time and need a solution urgently. Any help is appreciated. My thanks in advance.

Ilker

ELC should have no problem with recognising a cell as simple as an inverter... I suspect the problem to be with your SPICE netlist. How are you generating it?

I generated mine by instancing all of the standard cells into a new schematic, without any pin connections, then exporting a SPICE netlist for this schematic.

I am generating the netlist exactly like that. In fact I used this tutorial in the beginning to learn that: http://www.ece.unm.edu/~jimp/vlsi_synthesis/tutorials/Cadence-ELC-Tutorial.pdf. My guess is the same that the subcircuit file is responsible, but I tried a lot of different subcircuit files, either modified or not changed at all, and still got this feedthrough pins. I also use the files directly available from university of utah, just to create one working flow, but even if the files are the same, I am still getting feedthrough pins. It will be a tremendous help if anyone saw anything like this.

Can you give an example of your inverter netlist? Something sounds dodgy. Are you providing the correct simulation model files for your technology?

First of all sorry for the late reply, couldn't check the thread over the weekend. Here is my inverter netlist as generated by the Cadence. I also use the model files of AMI06. I cycled through a lot of different model files but that made no difference. If I can get everything working, I intend to use tsmc018 technology though.

// Generated for: Spectre
// Generated on: Aug 31 18:05:16 2006
// Design library name: tutorial
// Design cell name: signalstorm
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: tutorial
// Cell name: inv
// View name: extracted
subckt inv A Y
\+1 (Y A vdd vdd) ami06P w=6e-06 l=6e-07 as=9e-12 ad=9e-12 ps=9e-06 \
pd=9e-06 m=1 region=sat
\+0 (Y A gnd gnd) ami06N w=3e-06 l=6e-07 as=4.5e-12 ad=4.5e-12 ps=6e-06 \
pd=6e-06 m=1 region=sat
ends inv
// End of subcircuit definition.


// Library name: tutorial
// Cell name: signalstorm
// View name: schematic
I1 (net1 net2) inv
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output" checklimitdest=psf
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub

Ok I had a look at your netlist. There are a few things that worry me:

1. Your inverter is characterized from an extracted view. Do you not have an original schematic view for the cell?
2. Another thing that seems strange from the netlist is your instance names... I am not sure, but \+1 and \+0 might be problematic for ELC. Try giving your instances names without special characters like NMOS1 and PMOS1.
3. Your power connections are not defined in the subckt declaration. Is this also not in your schematic? Mine looks like: subckt inv A Y vdd vss.

These are the only things that seem to be incorrect to me. First try to fix the netlist by using schematic views instead of extracted views in your top schematic. This may fix all of these problems.

Well I do not have a schematic view, actually I have for this inverter, but I don't have one for the real cells I would like to characterize. The reason is that we are doing some experimenting with layouts and not always sticking to drc rules (we are not going crazy though they can be still perfectly fabricated), so trying to have an LVS match is just a waste of time for us at this point. I have the required functionality for my cells though and a physically extracted view is what I need in the end, in order to get a realistic characterization. The examples I follow all used the extracted views and got it working.

Anyway I tried changing the names if instances like you said and added vdd an gnd to their declarations and still couldn't solve the problem. I will go ahead and try with a schematic netlist just to see how it goes, but like I said, I don't think I will have a schematic view for the real thing.

You could always create the schematics after finishing the layout

Hello ioztelcan,

did you solve the problem?
If yes, could you please explain a little, since I'm having the same problem...
Kind regards!

Hi hans_r,

I unfortunately could not resolve this problem completely and it still haunts me to this day. I made it kind of work by accessing a file with simple i/o information and changing it myself. I do not remember the names but just dig through the folder ELC created until you find the file named port or ports. Open it and change the feedthrough pins with In and out depending on your circuit. It is a really simple file with just port information so don't worry about screwing things up, and even if you do you can just start over. After you save that file run ELC one more time to ensure it sees the ports as they are and continue the characterization.

This does not solve the problem completely however, it just enables ELC to give signals to proper ports. I had problems with intrinsic capacitance and resistance calculations later on and I blame this stage. Maybe you won't get them later on though. Working with Cadence is working with a weird Pagan God you never know what it really wants and things that you can't explain happen all the time, it's exhausting.

Anyway, I hope you get it working. If you do by any chance I would like to hear about your solution. Here is a link that helped me a lot when I was working on that dreadful characterization project: https://www.cs.utah.edu/~elb/cadbook/

Good Luck,
ioztelcan

Hi ioztelcan,

I fixed the problem!
You should use a bool file to help ELC with the cell recognition. To make a bool-file, check the ELC user guide appendix D.
After preparing the database, you should run the db_gsim command with the bool-file, in stead of using the db_gate command, like this:
db_gsim -bool inv.bool -force

inv.bool looks like this:
INV1, "inverter size=1",
Y = NOT(A);


After this, all problems were solved for me, I can easily run the db_spice command and come out with perfectly good lib-files.
Kind regards,
hans_r

That is great! I don't have the means to try if it works on my project right now but there is at least one well documented solution on the web now. Hope it helps someone, someday.

Best,
ioztelcan