encounter DRC violations

Hello everybody:
When I finished P&R Layout in encounter, I use Assura to do DRC. However I find the following violations. Do you know how to figure out them ? Do I need to do some special configurations in Encounter? I am using the AMS-H35B4-ThickallMeta tech.
Best Regards

[4] INFO : standard pad met4 4 stack
[10] rvia2 INFO : rvia2 does not open met2/3 for drc
[2] BAD_SUBSTR_SUBTAP_FLOAT_ERC
[8] NWD_R1 : (NWD and not DIODE) must be connected in parallel to a similar diode in a device which is compared in LVS
[1081] INFO: hot nwell
[51] NW_W_2 Minimum HOT_NTUB width = 3
[4100] OD_C_3 Minimum NDIFF to HOT_NTUB spacing (without PTAP in between) = 2.6
[1] PO_R_1 Minimum density of POLY1 area [%] Density = total poly layer area / chip area Recommended dummy structures are 5um * 2um rectangles with 2um spacing. They should not be placed on active devices. = 14
[1] M2_R_1 Minimum density of MET2 area [%] = 30
[4] AMW0 Maximum METx width = 35 metal2
[96] AMW0 Maximum METx width = 35 metal3
[96] AMW0 Maximum METx width = 35 metal4
[8] AML1 AML2 Minimum slot length = 30 Maximum slot length = 300 metal2
[15] ERC Warning: Floating met1
[24] ERC Warning: floating gate not connected to s/d, pad, pin or resistor
[80] BAD_PDIFF_MULTCONN_ERC
[4] pdres_all_g1_pdres_all_wexp: RDIFFPS_G1: Minimum number of squares = 5
[1] # INFO: H35B4/H35B3 ASSURA DRC DECK (REV12 DATE 31-May-2012) REV5 120V Last modified 19-Jul-2012 #

you could read the DRC report from Assura in Encounter and fix them by hand.
but first, the design from Encounter is DRC clean?
if yes, you must understand why these error are not seen by encounter.

Hello. The reason is that I forget to create label on power pad. In LVS , I have a new error.
"unstable device for NMOS_device_MOS_1" Do you know the reason