Enable signal for clock gating technique...

[blaze1200]

Hi,

Can I use the reset signal of a flop as the enable signal for clock gating technique? Please advice...

Thanks....

 

[lostinxlation]

Depends on how you use it.
Elaborate.

 

[blaze1200]

The design is as attached...
Is it possible to use the rst input signal of the flop as enable signal for clock gating?

 

[phoenixpavan]

Hi Blaze,

The attached figure is fine...u can use it

 

[jeevan.life]

It looks good..Probably you can go ahead...

 

[laglead]

It depends on if rst signal is synchronized or not. At the time rst is released (DFF become not reset) you do not hope clock toggle the flip flop at that time because it may induce race. So generally you should add constraint between clock and rst. Or rst can be synchronized before sent to clock gating. rst for flip flop could still be asynchronous.

 

[blaze1200]

Thanks for the input phoenixpavan...

---------- Post added at 01:31 ---------- Previous post was at 01:30 ----------

Thanks jeevan

---------- Post added at 01:32 ---------- Previous post was at 01:31 ----------

Thanks laglead ...