emulation and timing not met in FPGA

sun_ray · Dec 5, 2013

Suppose we are running emulation with FPGA and find the timing of 550 MHz is not meeting on FPGA. What can we do then to do the emulation?

shaiko · Dec 5, 2013

If the purpose of your FPGA design is only functional verification - why do you insist on running at such a high frequency?
Just synthesize your final design on the FPGA and make sure it functions properly. Than do a thorough timing analysis on your ASIC synthesis tool.

With your RTL code being the same, everything should work properly.

emulation and timing not met in FPGA

sun_ray

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shaiko

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emulation and timing not met in FPGA

sun_ray

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shaiko

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