Emulating TTL with an MCU

[neazoi]

Hi I try to investigate if the octal buffers in this project https://github.com/skiselev/micro_8088 can be replaced with an MCU and emulate their behaviour with software. Ok these have s.triggers inside and they are fast but in this project the speed of the MCU should be enough. Shall I try it or not even think about it?

 

[betwixt]

If you mean the 74F573, 74F244 or 74F245 devices, yes in theory if you can find an MCU running at a few GHz clock rate.
They are 'Fast' 74 series because very short propagation delays are necessary, to achieve that you would have to read and write through an 8-bit MCU port at equivalent speeds and that would require an unreasonably fast clock rate.
As they are only buffers, it doesn't make sense to use software at all.

Brian.

 

[neazoi]

If you mean the 74F573, 74F244 or 74F245 devices, yes in theory if you can find an MCU running at a few GHz clock rate.
They are 'Fast' 74 series because very short propagation delays are necessary, to achieve that you would have to read and write through an 8-bit MCU port at equivalent speeds and that would require an unreasonably fast clock rate.
As they are only buffers, it doesn't make sense to use software at all.

Brian.

They may be able to be replaced by slower types https://github.com/skiselev/micro_8088/blob/master/Building_Instructions.md eg. LS series. He says it might work. I do not mind reducing the clock to 4MHz even less from the "turbo" 10MHz in order to achieve that.
I am thinking of software so that I can emulate their ENABLE or latch behaviour.
Yes this is kind of weird, but I am thinking this as a way to reduce the number of chips even more.

Maybe I could try to do it with simple discrete circuits, like I did here? **broken link removed**

 

[KlausST]

Hi,

a bit unclear.

In headline you talk about "emulating TTL":
--> TTL = transistor-transistor-logic ... which more or less describes the ouput (and input) stage of a logic device.

in text you talk about "replacing octal buffers":
--> do you mean the SN74F573N ICs?
If so,
* why don´t you simply write you "want to replace SN74F573N with an MCU" and avoid guessing?
* SN57F537N is a "octal latch", not a simple buffer. And they have no schmitt-trigger inputs..

--> do you mean the SN74F244 ICs?
If so,
* why don´t you simply write you "want to replace SN74F244 with an MCU" and avoid guessing?
* But they have no schmitt-trigger inputs..

****
You write you want to replace it with an MCU. Which MCU? There are so many... with different specifications, some may suite some may not.
Do you want a "pin-to-pin" replacement? Or what is your idea?
You say "the speed of the MCU should be enough". How do you know? Where are the timing requirements? A 74F244 has a delay of about 4ns from input to output. I´d say about impossible to achive with software....
many MCUs may have trouble with 1000 times slower (= 4us)

Maybe you should give more (and clear) details...

Klaus

- - - Updated - - -

Hi,

They may be able to be replaced by slower types ... eg. LS series.

I assume they know why they used the fast ones.... instead of cheap, low power, good available, but slower LS family logic ICs.

Yes this is kind of weird, but I am thinking this as a way to reduce the number of chips even more.

A single PLD could replace all the logic ICs easily.....an FPGA even could include the whole 8088 ...

Klaus

 

[neazoi]

Hi,

a bit unclear.

In headline you talk about "emulating TTL":
--> TTL = transistor-transistor-logic ... which more or less describes the ouput (and input) stage of a logic device.

in text you talk about "replacing octal buffers":
--> do you mean the SN74F573N ICs?
If so,
* why don´t you simply write you "want to replace SN74F573N with an MCU" and avoid guessing?
* SN57F537N is a "octal latch", not a simple buffer. And they have no schmitt-trigger inputs..

--> do you mean the SN74F244 ICs?
If so,
* why don´t you simply write you "want to replace SN74F244 with an MCU" and avoid guessing?
* But they have no schmitt-trigger inputs..

****
You write you want to replace it with an MCU. Which MCU? There are so many... with different specifications, some may suite some may not.
Do you want a "pin-to-pin" replacement? Or what is your idea?
You say "the speed of the MCU should be enough". How do you know? Where are the timing requirements? A 74F244 has a delay of about 4ns from input to output. I´d say about impossible to achive with software....
many MCUs may have trouble with 1000 times slower (= 4us)

Maybe you should give more (and clear) details...

Klaus

Wow relax man
Just read post #1. Regarding the speed, I said "should" it doesn't mean I am correct. The second link on post #3 says LS might be ok. I guess, if decreasing the CPU clock, LS might work fine, but that's a guess without numbers. After all it is 10MHz at max. I was thinking of an atmega644 or similar low clock MCU.

 

[betwixt]

Neazoi, there are two factors at play, one is the propagation delay (time between a transition or control change at the input reaching the output) and the other is the rise and fall time of the waveforms. Both are faster in the 'F' series TTL devices but at 10MHz clock it may still be possible to use 'LS' series with reduced safety margin. The system clock speed isn't the only consideration when deciding what buffers are needed, the relative timing of different signal paths is also very important or you face 'race' problems. (as in speed - not ethnicity!)

As Klaus and I stated, to use an MCU is impractical. Firstly you need one with many input and output pins, for example to replace the '573 devices you need 33 I/O pins which immediately limits what is available and to make a simple latch you need one read operation to check the latch input, a decision, maybe a second read from the data input and then a write operation to the output. Each of those would take several clock cycles at MCU speed.

You can simplify it by incorporating the logic into a PLD and keep the high speed that way but for the same reasons, you might find it hard to find a device with enough resources that is still usable without automatic assembly machines.

Brian.

 

[FvM]

A small microcontroller will never be able to emulate logic gates in a useful speed range (e.g. > 1 MHz). If you want variable logic function, think about CPLD or give it up.

 

[KlausST]

Hi,

Wow relax man

I´m relaxed. But I´m surprised by this much inconsistency.

OK - I could have wirtten only one issue in a post.... but then the thread will become lengthy...

All I wanted to say: Review the whole idea. Try to get specifications. Try to avoid guessing. Try to be more unambiguous.

Klaus

 

[neazoi]

Hi,


I´m relaxed. But I´m surprised by this much inconsistency.

OK - I could have wirtten only one issue in a post.... but then the thread will become lengthy...

All I wanted to say: Review the whole idea. Try to get specifications. Try to avoid guessing. Try to be more unambiguous.

Klaus

Thank you. I could just try it and see if it works. Maybe a discrete components solution would be better as I said, and maybe faster. Sometimes things are more relaxed than the designers have in mind. For example I do not know why the F series is needed in <10MHz clock. It won't harm but it may not be needed. I guess the answer is I should try and see.

 

[betwixt]

You are missing the point. The clock speed only determines how many instructions the 8088 can execute in a given time, the rest of the system has to comply with timing constraints which probably still need the fast responses. The electrical operations still run at high speed, all the clock does is set the pace they happen.

I would guess LS series would work in that design because it seems to have static memory devices which do not need refresh signals but if the more common DRAMS were used, either in the SBC or in the expansion slot, I think you would run into problems.

Brian. (who is always relaxed :| )

 

[neazoi]

You are missing the point. The clock speed only determines how many instructions the 8088 can execute in a given time, the rest of the system has to comply with timing constraints which probably still need the fast responses. The electrical operations still run at high speed, all the clock does is set the pace they happen.

I would guess LS series would work in that design because it seems to have static memory devices which do not need refresh signals but if the more common DRAMS were used, either in the SBC or in the expansion slot, I think you would run into problems.

Brian. (who is always relaxed :| )

All right I see...
There is a question that comes to mind, how can the clock run at a lower speed and operations happen at a higher speed? Maybe you refer to the rising and falling electrical signals properties?

 

[KlausST]

Hi,

let´s do an example with a simple SRAM READ where the data is additionally buffered

The microcontroller sends out address and control signals ... thes traval all the way through your PCB and ICs ... then the data need to be at the microcontroller boefore the it reads the data in.

uC (address and control signals out) --> wiring (delay) --> SRAM (address in, data out. access delay) --> wiring (delay) --> buffer (delay) --> wiring (delay) --> uC data in (setup time)

You see it takes a lot of (delay) time from address_out to data_in of the microcontroller.
Every microcontroller datasheets contain the specification how long a signal may take...

Now let´s say: (example values)
* wiring delay = 2ns
* SRAM access time : 65ns
* buffer delay: 10ns

Then the total signal takes: 2ns + 65ns + 2ns + 10ns + 2ns = 81ns

Klaus