flote21
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Hello everbody,
I am in a very big project with an ALTERA FGPA Cyclone IV. This FPGA is going to control several systems and every system has its own configuration file sent by SPI protocol which it is already implemented like a VHDL module in the FPGA. In the start up of the system, the FPGA is sending the intial configuration file for a default hardware which is the most commun. This configuration file is stored in a FIFO memory with the possibility to be modified "on fly" thanks to the "IN SYSTEM MEMORY CONTER EDITOR" tool provided by Quartus II SW. So if the Hardware changed we can use this tool to change the initial configuration SPI file....
But we don't want to use this tool and we want to change the initial SPI config file in the FIFO using the a command recevied by ethernet protcol (The FPGA has also implemented a Ethernet module to communicate with a PC). This command is going to be read by the FGPA and accordint to this we will change the initial configuration file.
See below the instantation of the FIFO memory:
As you can see there is a GENERIC ==> "INIT_FILE" where you have to indicated the path of the file you want to load. And it is this path what I want to modify "on fly" when I receive the ethernet command...
Any idea how to implement this?
Thanks.
I am in a very big project with an ALTERA FGPA Cyclone IV. This FPGA is going to control several systems and every system has its own configuration file sent by SPI protocol which it is already implemented like a VHDL module in the FPGA. In the start up of the system, the FPGA is sending the intial configuration file for a default hardware which is the most commun. This configuration file is stored in a FIFO memory with the possibility to be modified "on fly" thanks to the "IN SYSTEM MEMORY CONTER EDITOR" tool provided by Quartus II SW. So if the Hardware changed we can use this tool to change the initial configuration SPI file....
But we don't want to use this tool and we want to change the initial SPI config file in the FIFO using the a command recevied by ethernet protcol (The FPGA has also implemented a Ethernet module to communicate with a PC). This command is going to be read by the FGPA and accordint to this we will change the initial configuration file.
See below the instantation of the FIFO memory:
Code:
i_SPI_INIT_RAM : entity WORK.SPI_INIT_RAM
generic map (
ADDR_SIZE => SPI_MEM_SIZE,
DATA_SIZE => SPI_MEM_RDOUT'length,
INIT_FILE => "../fit/SPI_INIT_RAM.mif",
INST_NAME => "SPIF"
)
port map (
clock => CLK ,
wren => '0',
address => SPI_MEM_ADDR,
data => (others => '0'),
q => SPI_MEM_RDOUT
);As you can see there is a GENERIC ==> "INIT_FILE" where you have to indicated the path of the file you want to load. And it is this path what I want to modify "on fly" when I receive the ethernet command...
Any idea how to implement this?
Thanks.
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