Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Emi suppression for component layer

Status
Not open for further replies.

Dinesh2017

Newbie level 4
Newbie level 4
Joined
Apr 13, 2017
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,348
Hi All,

I am working on high speed board design .my doubt is avoid emi problem i provided full solid copper plane in external layer after completing routing.whether work out this method it will create any problem in design.
any alternate method.can you provide suggestion.



Thanks and regards,

M.Dinesh
 

If the top layer is "full solid copper plane", how will there be components?

Flooding the outer layers with ground copper can make sense under circumstances, but you need sufficient vias to connect it. You find ground pours with via fences e.g. in RF PCB.
 
Hi Thanks for your reply.

i understand what your saying. whether this is applicable only high speed and rf or low speed signal board i can implement.
can you give some ref note.
 

Read info from the likes of Henry Ott, Ralf Morrison, Keith Armstrong (EMC UK)...
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top