EMC/ SI simulation software for pcb design

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plengde

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Hi,
Can anyone please suggest best simulation tool for EMC / SI simulation for pcb? Circuits are not very complex, mixed signal, with frequency less than 25 MHz. Need to evaluate near and far field effects, No shielding is to be considered as for now. HyperLynx, Ansys or CST PCB? any other option? Has to be compatible with Cadence Allegro for Layout.
Thank you.
 

Why SI simulation for 25MHz its not mega fast, though rise time has a big effect, but most circuitry at that speed can be thrown down. EMC is down to you as a designer, read up stuff by Henry Ott (Ott Consultants) and for sig integrity Howard Johnson.
For Allegro:
**broken link removed**
 

Thanks for reply!
Yea I know 25 MHz isnt too fast and our designer team has taken care of basic EMC rules since start. I am new in team. Apparently earlier boards failed in EMC. So these many precautions. Boards will be connected to FPGA for further controls. Does that matter?I have to take care of radiated and cnoducted EMC. Is this tool any good? I dint find much info on it?
**broken link removed**
Boards will be receiving analog ip in noisy industrial environment. Will it help as a tool or should I cosider EMI filters?
Thank you.
 

I cant comment on the software as I have never used it.
EMI filters, ferrites etc are always a good choice when things are going or coming off board, most designs I do have an some sort of EMC, ESD protection for connectors.
As to EMC software, my view is learn all you can from people like Henry Ott, Keith Armstrong etc and lay out the board correctly so minimising any EMC problems. I very rarely have EMC problems with my layouts and do a lot of high reliability stuff and SMPS layouts, but I have spent 25+ years studying and learning...
The basic EMC thing to learn is to understand dipole structures on a PCB layout.
 

Thanks for the reply!
I will take things you mentioned in cosideration. Can you please suggest where I can find good material on ground conductance and Rejection Ratio?
 

FPGA has a "downside" that many people do not consider: even when running @25MHz the FPGA is still a device that has output structures capable of driving into the hundreds of MHz, with rise and fall times to match. And it is those parameters that matter with SI and EMC (which is basically the flip side side of the same coin).

This can be partially resolved by setting drive strength of your IO in the FPGA, but it's something you need to be aware off...
 

Hey,
Thanks for the reply. I will look into the matter. Any advice on managing conducted susceptibility?
 

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