Embedded Systems Design Methodology & Used Model/Languag

Hi,

I am a newbie in Embedded Systems. I am trying to understand the methodology of embedded systems not to design them but to verify them.

So my questions to you, the embedded systems experts:

1) In practice, when you start to design a new project of designing an embedded system, do you start immediately with a concrete languages such as C/ASM for the software parts and such as Verilog/VHDL for the hardware parts? Or do you start with a higher level model for the whole system such as CoDesign FSM (Polis) or SystemC or UML or what?

2) What do you want to verify for your embedded systems? Let's assume that you design a low-level device driver for an embedded systems; What do you want to verify: the real-time behavior of the device-driver in related to the hardware device?; And how are you verifying your device driver now?: using debuger, co-simulator?

3) What are you willing to do when verify your systems? Do you mind using the other model languages (high-level) such as SDL/UML/CFSM to model your systems in order to verify them formaly? Or would you like to just give your C-codes and HDL-codes to the verification engineers and ask them to verify the desired properties.

I would like to thank you in advance for your answers. They would help me much.

Re: Embedded Systems Design Methodology & Used Model/Lan

Hi

When I start a new design i'm trying to relay on a previus design who is working and have less bugs
the easy way is to use a demo bord for referance
For most of the microcontroller/processor demo board is avaliable some for low cost
I'm trying to use C language as software development language beceause is HLL
(High level language) and VHDL for hardware

All the best

Bobi