electromigration in ic circuits

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anujsantro

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latch up in cmos

can anybody tell me, what will be the effect of reducing well and substrate resistances on β(loop gain) of parasitic transistors formed inside a cmos.
 

latch up in cmos

Nothing.

You're not killing the transistor gain per se, you are increasing
the amount of current required to initiate & sustain the SCR
conduction. The parasitic devices themselves are not altered
unless you are changing dopings or spacings (lateral BJT base
width).
 

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    anujsantro

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Re: latch up in cmos

"Reducing well and substrate resistances" is equivalent to "changing their dopings", isn't it?
 

Re: latch up in cmos

yeah, it means doping has been increased to reduce the resistances, say n-well doping has been increased, it means beta of pnp vertical transistor has been reduced,coz Ic is reduced. isn't t?
 

Re: latch up in cmos

I got a doubt >> is the increasing doping level for well a measure to avoid latch up??

what other effects arise for performance of CMOS by increasing the doping level for well.


--anuj.joamon
 

Re: latch up in cmos

anuj.joamon said:
I got a doubt >> is the increasing doping level for well a measure to avoid latch up??

what other effects arise for performance of CMOS by increasing the doping level for well.


--anuj.joamon
Click to expand...

IT will certainly give latcup immunity by increasing the recombinations of electrons in well region.. reducing beta of PNP transistor.. But at the same time PMOS threshold will be increased.. .. You can use eipitaxial layer along wiht highly doped P substrate as alternative..
 

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    anujsantro

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latch up in cmos

Does it mean that if doping of substrate as well as n-well has been increased to make resistances smaller, will it reduce beta of transistors?
 

Re: latch up in cmos

anujsantro said:
Does it mean that if doping of substrate as well as n-well has been increased to make resistances smaller, will it reduce beta of transistors?
Click to expand...
No. As Dick Freebird stated above: "You're not killing the transistor gain per se, you are increasing the amount of current required to initiate & sustain the SCR conduction." See the extract from Rincón-Mora's CMOS Technology course below.
 

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