[SOLVED] Electromigration concerns -- how to compute Blech length, practical effect?

I have a set of signal wires that, due to layout concerns, are probably going to need to be driven with unidirectional current. Specifically, the NFET pulldown and PFET pullup are about 30um apart on a wire which is 400um long and 0.25um wide (min-pitch). Wires are Al (pre-Cu process).

I'm aware that driving a signal wire unidirectionally is bad news from an electromigration standpoint. Does anybody have any helpful pointers on practical information on how this affects reliability? Or whether or not this is within the Blech length? All the foundry provides is maximum current levels, which I'm well within.

The only reason I'm considering doing this is that the application is a bit unusual -- it can tolerate quite a lot of failure. If this design choice means a 5% failure rate over the first year, that's actually okay. If one of these wires fails it only kills about 1% of the chip, and we already have to be able to route around stuff like this for other reasons. Think of the device-reliability tradeoff in an SRAM-with-ECC -- that would be a reasonably good approximation of the reliability requirements. Most foundries give you more-relaxed design rules you can use for SRAM as long as you're prepared to tolerate a small number of failures. This isn't an SRAM, but the device-level reliability requirements are very similar in that respect.

Unfortunately I'm a bit spooked by the stories about Western Digital's electromigration problem that caused 90% of a particular model of hard drive to fail all within a 6-month window.

The line length at which EM will not occur, is pretty short.
I don't know what it is in any particular technology, but
people make electromigration-mode fuses at lesser length.

If you are within ratings, you should be fine, provided those
ratings include random defectivity like notching, and not-
random but variable things like thinning over topography.
Back in the day we used to include these in the high-rel
rules for calculating current density, but I observe them
to be missing in modern day kits I use.

A line failing within a 6-month window, under normal use,
when EM rules are usually set for 10-year range of service
life at extremes of temperature, is an extreme physical
design miss.

Now if this is CMOS, is your current even DC? It would
seem not, or trivial current, at 0.25um. Are you time-
averaging the current for purposes of analysis?

dick_freebird said:

people make electromigration-mode fuses at lesser length.

Click to expand...

Ah, thanks, that's the sort of practical indication that helps.

dick_freebird said:

Now if this is CMOS, is your current even DC?

Click to expand...

Well, not in the sense of purist static CMOS where every node has a perfectly dual NFET PDN and PFET PUN, with exactly the same gate inputs. But neither is it anything weird like current-mode logic or anything like that.

Are you time-averaging the current for purposes of analysis?

Click to expand...

No, I'm using peak current.

Thanks again!!