Re: Electrolytic capacitor ESR not specified in datasheets, can it be estimated?
Ripple voltage at low frequency is governed by the ratio of source to load impedance. The Caps are distributed in parallel with the source voltage impedance. Regulators have a low ESR that is reduced by the DC feedback gain , which rises to the internal ESR and distributed ESL with frequency due to gain-bandwidth of the regulator if used. otherwise an unregulated source has the ESR each part in series, ( winding Rs, diode pair ESR, and any series R,L impedance.
The Caps are rated at 120 Hz since a bridge doubles the line frequency. The D or δ = tan δ for low values is simply the ratio of ESR/Xc where Xc = 1/(2pi*120Hz*C[F].
So you can calculate ESR = D*2pi*120*C
The max ripple current(rms) is given with an internal temp of 85'C so you can compute the device thermal resistance if you wish using 60 deg C rise over Power dissipation (Irms²*ESR) .
If there is a switched or dynamic load RL with a capacitive or inductive load and associated ESR's you can estimate the ripple voltage from the ratio of load ESR * I step. This ripple is reduced by the often same or lower ESR ceramic caps at a frequency between the SRF of the e-cap and the ceramic caps.
Often this is overlooked and designers will either over-design it ... Or under-design it and fix it later with low ESR caps and/or LC filters and/or RF caps and/or distributed dielectric C in the PCB substrate.
So it all depends on your dynamic step current, ripple requirements on which components you choose in a design.