Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Electric voltage withstand capability of PCB layers.

Status
Not open for further replies.
T

Techman_7

Full Member level 2
Full Member level 2
Joined
Dec 21, 2013
Messages
137
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,298
Activity points
2,412
I am working on 11kW electric vehicle on-board charger.
With the PFC output voltage (DC link) = 800VDC (considering ripple, peak voltage = 840V), we have made layout such that +VE DC link & -VE DC link are overlapping on layers in multilayer (6 layer) PCB. It forms a PCB capacitor at such high voltages. So, is it recommended or is it fine with such layer structure.

How much voltage the two adjacent layer of FR4 PCB can withstand?
 

Sort by date Sort by votes
Substrate thickness matters. For functional isolation (not safety related), I would use minimal 8 mil (0.2 mm) substrate. Preferably composed of 2 prepreg layers. CAF (conductive anodic filament growth) aware design might require thicker substrate.
 

    T

    Techman_7

    Points: 2
    Helpful Answer Positive Rating
Upvote 0 Downvote
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top