ehternet hardware testing and debugging?

[evilheart]

i am working on an embedded systems ethernet project , we are using micorchip ENC624J600 , i didn't design the PCB yet ,
but we have lack in components as we bought it from abroad and we don't have time to rebuy if they were damaged on failed protoypes , i have read several tips about designing PCB layout for ENC624J600 from the data sheet and other resources , i think the brief of it :
keep the TX and RX tracks straight and short , run them in pairs and make the pairs away from each other and every thing else

of course the same goes of course to SPI lines as well

is there other things i should consider ??? is there some standard tests to each part of circuit ??
the UART can be tested by loop back by i don't think that will work here because of addressing and all the complex stack stuff ,

how can i test the magnetics ??

is there some guide line for such applications ?

 

[bsprajc]

The PHY has an internal loopback mode. That would help you determine if the part is configured correctly from a software point of view.

For an external loopback test, you could cross TX and RX on the other side of magnetics, and then send ethernet broadcast packets (all FF:FF:FF:FF:FF:FF in the MAC header destination field) and see if you receive the packet back. It's probably not a sufficient test for a production product but it would at least indicate signs of life.

I was unable identify any status registers which would indicate packet error counts, which are typical of general ethernet nics. Too bad 'cause those could be some corse indicator of signal integrity