Efficient way to construct OR/AND gates

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nervecell_23

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Is there any way I can code an OR/AND gate more efficiently?

For instance:
Code: 
wire in_1, in_2, in_3;
wire out_1, out_2;
assign out_1 = (in_1||in_2||in_3);
assign out_2 = (in_1&&in_2&&in_3);

Three inputs is fine for the above example, but what if I've got 500 inputs?
 

If you've got 500 inputs, then you probably want to use an array in and a for loop or some function to gate them

But if you have a 500 input and gate, you're probably doing something very wierd, or very wrong.
 

just 500 inputs. I did consider using array and for loop, but I couldn't figure out how to code within loop.
Could you advise?
 

Code Verilog - [expand]
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bit [499:0] in_1;
 
bit out_1;
 
for(int i = 0 ; i < 500 ; i++) out_1 = out_1 & int_1[i];
 

Actually TrickyDicky's example is not quite correct for what you want to do.

Code Verilog - [expand]
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wire [499:0] in_;
// for ANDing 4 inputs together and generating an out for those AND'd inputs
wire [500/4-1:0] out_;
 
integer i;
for (i=0;i<500/4;i=i+1) assign out_[i] = &in_[4*i +:4];


&in_[3:0] means bitwise AND the bits together (i.e. it's equivalent to in_[3] & in_[2] & in_[1] & in_[0]). The [4*i +:4] is a bit slice of +4 starting at 4*i so first itteration will give 0 resulting in the slice [3:0], the second itteration will start at 4 giving a slice of [7:4].

|| and && are logical operators and behave the same for single bit operands but are not the same for vectors.

- - - Updated - - -

Actually if all you wanted to do was AND or OR all the inputs together then Tricky's code would do the job, but the code below would the the "right" way to do it.

Code Verilog - [expand]
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wire [499:0] in_i;
wire out_1, out_2;
 
assign out_1 = &in_i;
assign out_2 = |in_i;
 

The above examples are good. As always make sure you understand what a verilog loop is actually doing - the synthesizer effectively unrolls the loop and will instantiate all necessary gates in parallel exactly as if you had typed one giant line with 500 &'s or |'s.

Also with that much logic make sure you understand the timing implications. It's going to be a slow operation (comparatively).
 

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