integrated buck converter layout
amriths04 said:
i am using AMS 0.35um CMOS technology to design a buck converter. the main switch and synchronous switch are both on-chip (along with the control circuitry).
1) my question is what layout architecture would you adopt for the main switches? the main switches are very wide and also must have a very less Ron (in mohms) (for better efficiency).
2) what metal layers to use for switch routing between fingers?
A general advice:
1. You need to decide on gate widths for low side and high side devices based on Rdson specs for your regulator. Split the total gate width into multiple fingers. Put the devices side by side, and arrange them so that the shape of the power device array (X to Y) is not too different from square-like shape.
2. Use low-level higher resistance metals (M1, M2,...) for vertical routing of source and drain nets, i.e. to direct the current vertically, towards less resistive higher level metals. If possible, use metal option providing smaller metal sheet rho for top metal layers. Use top (low resistive) metal layer for lateral routing - i.e. to direct the source/drain current going up from the transistors laterally towards external connections (bumps, wirebonds,...).
3. The metal routing and wirebond connections should be "balanced" - meaning that current should be distributed as uniformly as possible over the power array area. The current in the devices should be uniform over the array.
4. Avoid sharp metal corners and narrowing in the path of high current - to void high current densities (current crowding) so as to avoid electromigration design rules.
5. Metal should be connected by as many vias (via arrays) as possible - to reduce resistance, and to avoid current crowding in vias.
6. If you need to do slotting (cutting holes in wide metal areas) - use such shapes/direction for the holes as to not the block the current flow.
7. Estimate Rdson value taking metal resistance into account - to make sure your Rdson value does not exceed a spec. This may be possible if your layouts are simple in shape. Otherwise, you need to use specialized simulation software. Forget about using standard extraction tools for this task - that's just a waste of time (this is a common conclusion among power device/IC designers/engineers).
8. Design carefully your sense device so that it matches the large array characteristics - the location of the sense device with respect to large array is critical.
9. Do a careful layout of the gate network - to make sure you do not have too high gate resistance, to avoid too large distributed RC delay effect (and thus dynamic current crowding), to avoid current shoot-through phenomenon, and also to avoid other parasitic effects related to gate switching.
These are just common sense guidelines, while there are so many degrees of freedom and variables in this problem that a specific solution and optimum may be different for different situations. As an example - the package that you use, wirebonds, leadframe, bumps/balls locations would put many constraints and "boundary conditions" on your design.
Max
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