Effects of Max Tran Violations

[vlsirocks]

max tran

I am trying to understand what will happen if I do not fix the max tran violations .
If my timing i smeeting and I have Max transition violations will my design work ? Please comment.

Thanks ..

 

[deh_fuhrer]

max tran violations

I am trying to understand what will happen if I do not fix the max tran violations .
If my timing i smeeting and I have Max transition violations will my design work ? Please comment.

Thanks ..

The violation of maximum output transition simply means that you are trying to drive a load with a weak driver. So the output voltage will not go upto the full level. Which eventually leads to logic failure...

 

[vlsirocks]

transition violations

Thanks Deh ... Other than upsizing the driver what are the other possibilities to fix the max tran violation ?
I guess the tool priority to fix the DRC is the highest and then the setup and hold violations are fixed ? Is my understanding correct ?
Please let me know.

Thanks ..

 

[eexuke]

encounter max_tran violations

The max violation may cause large short circuit power since both PMOS and NMOS would be on for a longer period of time.

 

[shelkerahul]

max_cap and max_tran violations

Another reason to fix transition violation is, Library will be characterized till certain value of transition. If you are exceeding that value then your library will not be having delay information in look up table for that transition. So whatever timing analysis you do, will not be correct, for particular instance.

 

[jitendra]

reason chip fail

Foundries specify limit on transition value beyond which they do not assure that chip will work, in other words transition violations may be one of the reasons for chip failure.
You can either increase drive strength of driving cell or insert buffer immediately after driving cell to fix transition violations.