Effective number of bits of 14-bit ADC

Hi,

That's a really good question.

I see two reasons:
* The chip designers were told to design a 14 bit ADC ... but failed to meet the precision
* marketing reasons: A 14 bit ADC is considered to sell at a higher price than a 12 bit ADC.

Klaus

Btw:
* you accidentally switched from ADC to DAC
* it's actually "precision", not "accuracy".

KlausST said:

Hi,

That's a really good question.

I see two reasons:
* The chip designers were told to design a 14 bit ADC ... but failed to meet the precision
* marketing reasons: A 14 bit ADC is considered to sell at a higher price than a 12 bit ADC.

Klaus

Btw:
* you accidentally switched from ADC to DAC
* it's actually "precision", not "accuracy".

Click to expand...

Hi ,

Then I have one more question related to this.Please see below.

We know that ADC 1LSB=Vref/(2^N) where N is the resolution of the ADC.

We know that ADC Effective number of bits (ENOB) is always less than the resolution "N".

When calculating 1LSB do I need to take 1LSB = Vref/(2^ENOB) or I need to take 1LSB=Vref/(2^N)

Regards
Hiyo

Hi,

newbie_hs said:

When calculating 1LSB do I need to take 1LSB = Vref/(2^ENOB) or I need to take 1LSB=Vref/(2^N)

Click to expand...

The ADC resolution afaik is always (decodable_analog_input_range / digital_output_range)
It never is ENOB.
Think about this: ENOB is not a fixed value, it also depends on your analog circuit, power supply, PCB layout... so the datasheet can specify ENOB only under the given test conditions.

Note:
I did avoid to write ...input_VOLTAGE_range because some ADC refer to "current" or other measures.
I did avoid to write "VRef" because some ADCs refer to
* VRef/2 or
* +/-VRef
* or VCC
* have built in amplifiers
* ...

Klaus

Above might help.


Regards, Dana.

ENOB is a function of signal-to-noise and distortion of the device.

ENOB = (SINAD -1.76)/6.02, SINAD is S/N and Distortion.

”extra bits” is not a marketing ploy, this is just how this stuff works. Yes, your 14 bit ADC has an ENOB of 12, but if you were to use a 12- bit ADC instead, your ENOB would probably be 10.

In a perfect, noise-free, INL- free, DNL-free, quantization-error-free world, your 14 bit ADC would have an ENOB OF 14-bits

Hi,

barry said:

”extra bits” is not a marketing ploy, this is just how this stuff works. Yes, your 14 bit ADC has an ENOB of 12, but if you were to use a 12- bit ADC instead, your ENOB would probably be 10.

Click to expand...

The OP states it has an ENOB of less than 12 ... so there never is an ENOB of 12.

***

For the given ADC ...
Can you give a physical, mathematical or any other scientific explanation of the benefit of the 2 LSBs?
I seriously would be interested, because my actual opinion is:
I´d say its not better than a good 12 bit ADC + 2 random bits. And random bits (unlimited number) you may also generate by software, no need to buy them.

Klaus

As DNL of the ADC is < 1 LSB, the 2 "noisy" bits give real resolution in some applications, e.g. acquiring small AC voltage with noise shaping filter.

For the OP reference library :




Regards, Dana.

FvM said:

As DNL of the ADC is < 1 LSB, the 2 "noisy" bits give real resolution in some applications, e.g. acquiring small AC voltage with noise shaping filter.

Click to expand...

Never thought of this.
I have to admit, it makes sense.

NOISE is given with 2.1 (1.05) LSB RMS .. so depending on noise distribution one can expect a noise amplitude of
+/- 10 .. 15 LSB pp (5..7 LSB pp).
So still the noise affects the 12 bits range.
This triggers my curiosity to find out how much information one can gain from the 2 LSBs.
I guess the noise shaping filter has a lot influence on the result.

Klaus

Also, if your use case allows you to make multiple samples in quick succession, then you can cancel out a bit of the noise by summing and averaging. You might get back a bit or two (but in my experience never the full stated number of bits of the ADC - there is ALWAYS noise).
Susan

KlausST said:

Hi,

The OP states it has an ENOB of less than 12 ... so there never is an ENOB of 12.

***

For the given ADC ...
Can you give a physical, mathematical or any other scientific explanation of the benefit of the 2 LSBs?
I seriously would be interested, because my actual opinion is:
I´d say its not better than a good 12 bit ADC + 2 random bits. And random bits (unlimited number) you may also generate by software, no need to buy them.

Klaus

Click to expand...

The benefit of the 2 LSBs is:

The ENOB is a function of the number bits. You’re not going to get 12 bits of ENOB from a 12 bit ADC, and you’re certainly not going to get it from an 8 bit ADC. The higher the number of bits, the higher the SINAD, and the higher the ENOB.

Hi,

I see an opinion, but no technical explanation. Your "8 bits" does not reference to the given ADC, which I asked for.
I asked for a good reason, because I already knew that one can not get a 12 bit ENOB from a lower bit ADC.

barry said:

The ENOB is a function of the number bits

Click to expand...

Only to a certain degree. It is a function of DNL and noise.
Thus I can't agree with your opinion "The higher the number of bits, the higher the SINAD, and the higher the ENOB".
Every (analog) signal (ADC input, ADC VRef, ADC (aperture) jitter, ADC linearity....) has a SINAD ... which can not be improved on the digital side.

And - what I learned now - the influence of DNL depends on signal amplitude. You get no DNL error without signal.
In opposite to noise - it will be there with or without signal. It will move bits with or without signal.

So as soon as noise is bigger than 1 LSB the output moves and thus you can apply filters to get the "statistical sub LSB" information.
(Similar to the "adding dither technique" to the analog signal on low noise ADCs .. to make the LSB move..to make the digital filters do their job)
From this point on .... additional bits have about no meaning. Noise dominates the error ... errors that can't be removed.

Digital resolution does not determine ENOB, it determines the "limit of ENOB". Noise also determines the limit of ENOB.
Total ENOB can not better than one of the former ENOB, because independent errors always add up, never subtract.

Klaus

Every (analog) signal (ADC input, ADC VRef, ADC (aperture) jitter, ADC linearity....) has a SINAD ... which can not be improved on the digital side.

Click to expand...

Not exactly. Using dither can mitigate DNL effects :




Regards, Dana.

Ap note discussing SINAD. https://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf

And we do all these calcs and algorithm mods, eg Averaging, ignoring the fact
most noise in our designs is highly correlated due to various clocks. Which modifies
ENOB.

Then we have the Allan Variance problem, attached.


Regards, Dana.

Hi,

I wrote: "which can not be improved on the digital side".

The dither is applied on the analog side.
But I see the benefit. Especially high bit order SAR ADCs suffer from DNL. Especially when multiple bits toggle:
for a 16 bit ADC: from 0x7FFF to 0x8000.

*****
If you use the dither method, you definitely add some "foreign signal" on the analog side. Thus in a signal to noise calculation you get a worse SNR value. But it may improve the DNL errors. On the other side you need to use low pass filters (to get rid of the "foreign signal"). So they reduce the useful signal bandwidth. A benefit on the one side, a drawback on the other side.

I wonder if one can say ENOB improved.
One definitely needs to match the test conditions. I.E. ENOB for the same signal bandwidth.
Would be an interesting task...
*****

Klaus

The dither is applied on the analog side.

Click to expand...

Yes and digital side in first case.....



Gains from dithering, example : https://www.ti.com.cn/cn/lit/an/snoa232/snoa232.pdf



Regards, Dana.

KlausST said:

Hi,

I see an opinion, but no technical explanation. Your "8 bits" does not reference to the given ADC, which I asked for.
I asked for a good reason, because I already knew that one can not get a 12 bit ENOB from a lower bit ADC.


Only to a certain degree. It is a function of DNL and noise.

Click to expand...

And noise is absolutely a function of number of bits. Of course, you can design a crappy 24 bit ADC with 16 bits of noise, but generally speaking, quantization noise is a function of the low-order bits flipping around. The more bits you have, the less those two or three LSBs matter, i.e, lower noise.

danadakk said:

Yes and digital side in first case.....

Click to expand...

I always tried to stay with the OP´s question, his ADC and it´s specifications.
Are you still discussing about the thread topic .. or is this some off topic discussion now?
Or in other words: Is this something you would recommend the OP to do?

I already agreed that dithering gives some benefit. (I put the "dithering technique" in post#13 in brackes, to mark it as side information, but not really topic related)

******
@barry
Don´t get me worng, I respect you as a valuable member, but I can´t agree (Or I don´t understand) to some of your posts:

barry said:

The ENOB is a function of the number bits.

Click to expand...

but you also wrote:

barry said:

ENOB = (SINAD -1.76)/6.02, SINAD is S/N and Distortion.

Click to expand...

so where is the
number of bits here?

**

barry said:

And noise is absolutely a function of number of bits.

Click to expand...

No. Quantisation_noise is a function of number of bits.
But not every noise in an ADC is quatisation noise.

**

barry said:

The higher the number of bits, the higher the SINAD, and the higher the ENOB.

Click to expand...

This simply is not true. You can easily find ADCs with a higher bit number but a lower SINAD and a lower ENOB than ADCs with a lower bit number.

**

barry said:

In a perfect, noise-free, INL- free, DNL-free, quantization-error-free world, your 14 bit ADC would have an ENOB OF 14-bits

Click to expand...

IF there was no quantisation error, then the ENOB could be infinite.
IF there was no quantisation error, then it could not be a 14 bit ADC. Indeed it needed to be an ADC with infinite bit number.
There is a clear realtionship beween quantisation noise (limit) and bit number. One can have the one without the other.

**

barry said:

Of course, you can design a crappy 24 bit ADC with 16 bits of noise,

Click to expand...

I could give you immediately (via PM) an example (ready to buy from a big semiconductor manufacturer) for this. This is no exception. And btw. I even use this ADC.
I did a lot of tests with this ADC, I know it´s limits. I know it´s performance. And thus I stay with my opinion that it is not better than a good 16 bit ADC plus 8 random LSBs.
**

barry said:

but generally speaking, quantization noise is a function of the low-order bits flipping around.

Click to expand...

I can´t agree.
Quatinsation error is the "remaining error" when "rounding" the analog value into an integer digital value.
If the input signal is DC, then the quantisation error is DC, too.
And quantisation error is not a real signal (so it does match, because I referred to a "signal" in post#13).
When all steps are equal in size then it is +/- 0.5LSB for each conversation.(peak to peak)

If... the bits are "flipping around", then this is a real noise signal (has nothing to do with quantisation). It could never be DC. "Flipping" and "DC" is contradicting.

And here is the point:
Applyinig this to the OP´s ADC:
* the quantisation noise may be close to +/- 0.5 x 2V / (16384) = +/-157uV pp (ignoring DNL. It may add 159uV pp with DNL worst case... by straight adding them. Indeed I think one needs to add them with square method, because they are independent)
* the input referred noise is closer to +/-12 LSB pp = +/-1460uV pp (depending on noise distribution)
Now add the noise (square method) and get a total of +/-1468uV pp (so the quantisation noise contributes negligible 0.64% to the total noise)
--> for 13 bits: 1493 uV pp, 2.2%
--> for 12 bits: 1589 uV pp, 8.8%
Most probably the part-to-part noise variation is higher than this 8.8%. (This why I call it negligible)

Now, like FvM wrote, including DNL things may be wore for small signals.
(with DNL 12 bits: 4x 157uV + 159uV = 785uV; 1658uV pp, 13.6%)

--> so even in worst case, using 12 bits out of 14 bits will make the ENOB worse by just 0.2 bits

Where is my mistake?

Attached dervitions.


Regards, Dana.

Hi,

The document says:
...the theoretical SNR of an ideal N-bit ADC: SNR = 6.02N + 1.76 dB....

I fully agree.

But we don´t talk about ideal ADC. It´s a real ADC with a real datasheet, with real specifications.

All the above formulae are correct.

Klaus