Sep 19, 2013 #1 F fly1 Newbie level 6 Joined Sep 1, 2013 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 67 Why does the logic effort and parasitic delay are not changed if the sizes of PMOS and NMOS of an inverter are changed? g=1 and p=1.
Why does the logic effort and parasitic delay are not changed if the sizes of PMOS and NMOS of an inverter are changed? g=1 and p=1.