Edge Trigger JK Flip Flop

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cincailo

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edge triggered jk flip flop

As I know that JK flip flop is to avoid the ambiguous case in SR (NAND latch) where S=R=1 is ambiguous. But I can't see from the internal circuit for JK flip flop that it can avoid ambiguous case when J=K=1. It seems it also need to depend which is start feedback Q or !Q, then only will get the toggle output. What happen when J=K=1 when initially Q=1 and !Q=0?
 

edge trigger

Hi cincailo,

NOTE: the more you look into flip flops the more confusing will it become.

Though, this one's quite easy.

The basic diagram of a JK flip flop is as shown.

So whenever J=K=1 and
Q=1 and !Q=0 >>[Set condition]
then,
the lower AND gate has 1 i.e activated.
even k=1
therefore a reset pulse is applied.
Meanwhile since !Q was equal to 0
The upper AND gate is disabled.
Thus 0 is passed to S input.
Thus S=0 and R=1
Thus o/p is of that a reset RS F/F
i.e Q=0 and !Q=1>> [Reset condition]

Thus it has changed from SET to RESET condition. Hence it is called as toggle state. when both j=k=1.

Try the other way round. j=k=1 and Q=0 and !Q=1

 

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