In my experience:
1.) any question about blocking/variable assign vs non-blocking/signal assign. (verilog/vhdl term). Basically, be able to explain the difference and discuss the two.
2.) any code example that shows a latch being inferred by accident. There are three common ways for this to occur.
3.) any question about setup/hold times, and how delays in the data/clock path can affect these numbers. There may also be related concept questions about clock-gating if you are looking at an ASIC design house. Basically, the clock buffer enable also has a setup/hold
4.) any question about metastability in FF's, and methods to overcome such a problem. This may also appear as an async signals question, eg "why can't an async signal be used in a state machine?"
5.) any question about longest paths, pipelining, and issues with feedback in pipelined applications.
6.) draw a block diagram of a system you have designed.
7.) any question about fifo depths and data rates. Particularly in cases where data bus widths/clocks change. An example might have data enter at 125MHz, 8b, transfer to a 100MHz 16b bus, then be output on a 125MHz, 8b bus. The key is that the 100/16 bus can process data faster, so it is ok. The transfer back to 125/8 is also ok because the original source can't generate data any faster.
8.) questions about serial interfaces may be possible.
9.) questions about memory systems may be possible.
10.) anything that is application-specific (cpu/dsp/etc...) to the company or job listing should be expected.
You probably won't be expected to know all of this, but the first three points are very common and you should do well on them. Question 6 is also common. Questions 4, 5, and 7 are more theoretical. If you do well on these questions you may make a strong impression. Questions 8, 9, 10 are more application-specific and for an entry level position you would likely not be expected to get correct answers.
All of these have been discussed online several times.