gezzas525
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Hi Iam doing ECRL low power design, and was trying to find a good way of calculating power dissipation in CMOS and ECRL circuits so that a comparison in power can be made between them. I used this method for calculating the power dissipation in the CMOS circuit **broken link removed**
however this method assumes the supply is fixed but in ECRL Iam using a ramp clock rise, hold, fall and wait. Where during rise it consumes energy and during fall it recovers it back into the circuit, obviously there is goin to be some loss being the difference between what went into the circuit and what was recovered. Can anyone find a way to apply this method, Ive tried integrating the supply in sections and multiplying the result with the rest of the equation.
THANKS
KLEOS
Hi Iam doing ECRL low power design, and was trying to find a good way of calculating power dissipation in CMOS and ECRL circuits so that a comparison in power can be made between them. I used this method for calculating the power dissipation in the CMOS circuit **broken link removed**
however this method assumes the supply is fixed but in ECRL Iam using a ramp clock rise, hold, fall and wait. Where during rise it consumes energy and during fall it recovers it back into the circuit, obviously there is goin to be some loss being the difference between what went into the circuit and what was recovered. Can anyone find a way to apply this method, Ive tried integrating the supply in sections and multiplying the result with the rest of the equation.
THANKS
KLEOS