Easy question about pipeline: Is this code synthesizable?

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flote21

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Hello!

I need to make a complex pipeline operation and I want to use this structure like a template:

Code VHDL - [expand]
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--process for calcultation of the equation.
PROCESS(Clk)
BEGIN
    if(rising_edge(Clk)) then
    --Implement the pipeline stages using a for loop and case statement.
    --'i' is the stage number here.
    --The multiplication is done in 3 stages here.
    --See the output waveform of both the modules and compare them.
        for i in 0 to 2 loop 
            case i is 
                when 0 => temp1 <= a*data;
                when 1 => temp2 <= temp1*b;
                when 2 => result <= temp2*c;
                when others => null;
            end case;
        end loop; 
    end if; 
END PROCESS;

I just want to know if this is synthesizable in an Altera Cyclone IV with quartus II. Would I have any problem with the FOOR loop?

Any other suggestions about pipeline templates are also welcome....

Thanks.
 
Last edited by a moderator:

I don't get the point of this, as the for loop always goes through all the cases each line of code (e.g temp1 <= a*data;, etc) exist. How is this a template? You might as just well write each of the temp1, temp2, and result lines separately and forget about the for loop and the case statement.

Regards
 

Hi flote21,

If you are using for loop as the repetition of the same operation, then it is not at all synthesizable. Such codes give the correct output only in simulation. If the for loop is for duplicating the instances or procedures then the code might synthesize. Anyways I'm not getting what exactly the intention of the code (its understood that you want carry out multiplication)
 

I feel there is no need of for loop here. If you want to do the temp1, temp2, result multiplication sequentially using case why need for loop simply use a counter to increment "i".

Regards
 

Hi,
I think You are trying to find the result = data*a*b*c within a single clock...
for this this wont work..
you are coding like a combination logic inside the clock...
You can either register the result inside the clock or make the combo outside the clock and register the result..
 

Actually they are trying to pipeline the operation data*a*b*c in three clock cycles. the problem is they approached this a so many software programmers approach VHDL/Verilog...using for loops as if they are just like for loops in a software language instead of like a hardware logic designer who thinks of the gates and logic that gets generated. I originally looked at the intent and felt it might be synthesizable. Don't know if it really is synthesizable as I didn't want to waste time trying to synthesize junk code.

This how you should pipeline using a for loop (done in Verilog as I'm not as fluent in VHDL):

Code: 
for (i=0;i<3;i=i+1) begin
  temp[i] <= i==0? a[i] * data : a[i] * temp[i-1];
end

a{i] are the values a, b, c. As the bit widths change as you keep multiplying the temp width needs to be adjusted each time through the loop, but I decided not to put the effort into doing that. I actually wouldn't recommend writing code like this as it doesn't make the code more legible. Someone having to pick up this code down the line will have to study it for a much longer time than the straight forward method of.
Code: 
temp1 <= a * data;
temp2 <= b * temp1;
temp3 <= c * temp2;

Unless we're dealing with >10 lines of this stuff it's much easier to see what is being done than the for loop version.

Regards
 

Hello people!

Thank you very much for your answer. According to this, the best way to do pipeline is:

PHP: 
process (clk)

begin 

 -- cycle 1
 temp1 <= a*b;
 -- cycle 2
 temp2 <= temp1*c;
 -- cycle 3
 result <= temp2*d;
 
end process;
 

Yes, if you add a clock edge sensitive condition
Code: 
if(rising_edge(Clk)) then
   temp1 <= a*b;
   temp2 <= temp1*c;
   result <= temp2*d;
end if;
 

That's right. I forgot it.

Thanks!!!




FvM said:
Yes, if you add a clock edge sensitive condition
Code: 
if(rising_edge(Clk)) then
   temp1 <= a*b;
   temp2 <= temp1*c;
   result <= temp2*d;
end if;
Click to expand...
 

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