Dynamic Power Optimization Using Look-Ahead Clock Gating Technique

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I recently read the paper : Dynamic Power Optimization Using Look-Ahead Clock Gating Technique and I have some questions :

The difficulty of glitches in gated design can be overcome using synthesis based design and the problem of sleep period can be reduced using Data Driven Clock Gating (DDCG) technique as given in Fig. 5

1. How exactly does glitches inside the gated design affect the clock gating mechanism ?
and why would synthesis-based design be able to solve this particular difficulty ?
What does it exactly mean by “sleep period” ? and how exactly DDCG technique reduce sleep period issue ?

2. As for LACG, what does it exactly mean by “By allotting complete clock cycle, timing constraints appearing in AGFF and DDCG techniques can be avoided” ?

3. What does it exactly mean by 1-(1-p)^k and p ?

4. Why would “A target FF depends on k>1 source FFs” ?

5. I refer to timing waveform inside Figure 3 of Shmuel Wimer’s paper : A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops , but I still do not quite understand what it meant by “After the tccq delay, XOR output gets corrupted and automatically turns to zero” ? I assume that tccq notation is similar to tpcq in the waveform below.