If you gate it off then you'll burn only static power when
idle, but now you toggle both that "gate" and the D input
when active.
In most modern DFFs the structure is tri-state inverter latches
(with set / reset injected by making some of them NAND or
NOR instead). D only toggles one inverter. CLK toggles many.
Reset does not stop CLK toggling all internal inverters, only
some.
A SPICE simulation from decent transistor level models would
be a good way to "what-if?" all of these various options.
A question is, how much power reduction is actually needed
and what's it worth to you in terms of -
- layout area
- design effort to add gingerbread
- simulation time to verify additional modes
- repeat last two until clean
- testability impact (can you test stopped-clock functionality
with decent coverage?)