Well, to connect the TigerSHARC link ports to FPGA,you first need to do the LVDS Tx and Rx modules. The Tx module can be done using the LVDS Tx function or by using the DDR IO. With link port clocks you need to align the data with the clock since data will be clocked at both the rising and falling edges of the link port clock. I suggest you align the data with the clock while transmitting LVDS data. If the SERDES in the FPGA has the data alignment option use it to align the data to the LVDS clock.
I'm doing the same thing with the Altera Cyclone series. Though these FPGA's don't have SERDES built into them, I generate the LVDS Tx and Rx using DDR IO and then connect them to the TigerSHARCs on one side and SERDES on the other.