A waveform with a time period Ts is at logic 1 for Ton durations and at logic 0 for Toff durations, such that Ton + Toff = Ts.
Duty cycle = Ton / Ts (%)
Typically, the digital signals are of 50% duty cycled.
I would like to generate analog signal with duty cycle >50% using verilog - A block for modelling my system.
I still don't understand what you mean by "analog signal with duty cycle"
In my eyes an analog signal has no duty cycle.
In my eyes "duty cycle" applies to digital signals only.
Guessing:
Maybe you want to
(A) generate a digital signal with fixed or adjustable duty cycle --> (B) then low pass filter it --> (C) to get an analog signal.
If so, this has been discussed many times before. Thus I recomnend to read through existing documents or watch youtube videos.
In case then still exists questions:
Give links to the documents you have read. Refervto sections.
We need to know what you expect from us:
Informations regarding A), B), C). Which informations?
I am not looking for circuit-based implementation. But in Verilog-A modelling of circuits. When a signal is sent out of the module it has options of delay, rise time, fall time, etc. But I would like to know if there is a way to alter the pulse width of the signal? I did go through the official document but found nothing.
Its data signal being clocked at the sampling frequency. So it has an input and output. I want the output to be off duty cycle > 50% so that the cross point of D and Dbar is a point higher than the centre point.
I will have a look at the post and see if it helps.
Posts #3 and #7 seem contradictory. I don't see how to specify a duty cycle for non-periodic signal. Please describe the intended waveform manipulation clearly.
I am trying to model current steering DACs in cadence. The digital signals driving the current switches need to have a high cross point. A high cross point can be achieved if the time that a signal stays 1 is greater than the time stays 0.
I would like to model this using a Verilog-A block.