During the execution of third machine cycle of IN 80H instruction, what will be the value at lower order address bus?

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During the execution of third machine cycle of IN 80H instruction, what will be the value at lower order address bus?
A. Data insufficient
B. There will be no third machine cycle.
C. 80
D. Depends on the location where this instruction is written.
 

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Hi,

A homework question.
But we don't know any context.We even don't know which microcontroller you are talking about.

Klaus
 

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Doesn't the 8085 data sheet show details of bus cycle timing?
Being honest, I haven't checked myself but every other MCU I've used has timing diagrams for memory and IO operations, especially where shared bus use is concerned.

Brian.
 

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