During Synthesi, if we won't provide a clock

Status
Not open for further replies.
M

manju540

Junior Member level 1
Joined
Mar 26, 2012
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,360
Hi,
During Synthesis if we won't provide any clock source .... .how tool will react where we are using clock in RTL design & how it converts in to netlist.
 

The design will still work , basically the tool will treat the block a synthesisable block and come up with gates. For example if you have 128 bit adder, the tool will come up with an adder with the smallest area. As you improve the constraints like speed and power the tool will optimize the speed of the design as it goes along. Nothing special about having a combination design in synthesis.
 

Synthesis tool knows DFFs and assume the wire connected to their CLK node is clock. So it won't create any buffers in this tree. But as was said it will work anyway.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…