dumping the code on FPGA kit ...

hello,
Can anyone tell me is there any posibility that code got executed in the fpga spartan3e kit, not executed on spartan3 kit eventhough succesfuly got dumped but not getting the output.


i will be very thankful for answering....

"Dumping code" means loading a FPGA configuration? It's actually about to impossible that the same configuration works with different FPGA types.

Nevertheless you should tell the exact devkit names.

FvM said:

"Dumping code" means loading a FPGA configuration? It's actually about to impossible that the same configuration works with different FPGA types.

Nevertheless you should tell the exact devkit names.

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sir actually when i dumped the code in spartan 3e 1200E kit i got the output on the kit, but when the same code dumped on spartan3 Xc3s400, pq208, i didnt get the output on the kit sir...

You cannot load the same config file onto different FPGAs. you need to recompile the code for the other device.

TrickyDicky said:

You cannot load the same config file onto different FPGAs. you need to recompile the code for the other device.

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sir i didnt understand what u said. can please tell me more clearly sir?

You need to say what code you're talking about.
Is this HDL code? or some C code you're loading onto a uP on the FPGA?

verilog HDL code sir...

Do you have the old verilog for the old board?

Do you have the bit stream for the design on the old board?

Do you know the exact board type of the old board? If so, what is this exact board type of this old board?

Do you have a link to this old board? If so, provide a working link to this exact board so people can see what board you mean. This to avoid any confusion.

Do you know the exact type of the NEW fpga you want to target? If so, what is the new fpga you want to run this on?

And of course you can provide any extra information that you think might help in getting you a solution faster.

gnseeta.btech said:

sir actually when i dumped the code in spartan 3e 1200E kit i got the output on the kit, but when the same code dumped on spartan3 Xc3s400, pq208, i didnt get the output on the kit sir...

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Did you recompile (resynthesize, place, route, sta, and bit file generation) the design from the Spartan3e 1200 kit for the Spartan 3 xc3s400 kit?

TrickyDicky said:

You cannot load the same config file onto different FPGAs. you need to recompile the code for the other device.

Click to expand...

gnseeta.btech said:

sir i didnt understand what u said. can please tell me more clearly sir?

Click to expand...

Tricky was asking if you used the bit file generated for the Spartan 3e 1200 kit on the Spartan 3 xc3s400 kit. Did you?

gnseeta.btech said:

verilog HDL code sir...

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Okay so this isn't some embedded uC design.

If you did recompile to the Spartan 3 device, make sure you are using the ucf file for the xc3s400 board, otherwise you may just be unlucky to have a pinout that is valid but doesn't match the kit.


I'd really like to know why posters like you insist on asking questions without giving any information that would allow someone to answer your question. Instead forum members have to pry the information from your heads with the jaws of life ;-) https://www.jawsoflife.com/en/product-type/combination-tools

i have verilog HDL code with me sir. I have done configuration to spartan3e xc3s1200e board i have got the output on kit. when the same code configured to saprtan3 xc3s400 device i m not getting the output.i have done the recompile( resynthesize, place, route, sta, and bit file generation) with respect to spartan3 board and i have used the ucf file for the xc3s400 board,eventhough i m not getting the output.

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i have old verilog for the old board.

i have the bitstream for the old board.

the old board is spartan3e ,xc3s1200 board .

the new FPGA i want to target is spartan3 xc3s400 board.

actualy im working on the project related to the Built in self test(BIST) concept, where i developed a code for this BIST in verilog HDL. now when i configure this code to xc3s1200 board i have got the output on the kit. when the same code configured to xc3s400 board i m not getting the output,but the code got successfully dumped on to the board.i have done the recompilation according o xc3s400 board too.

im not able to undestand where im doing mistake.

ads-ee said:

I'd really like to know why posters like you insist on asking questions without giving any information that would allow someone to answer your question. Instead forum members have to pry the information from your heads with the jaws of life ;-) https://www.jawsoflife.com/en/product-type/combination-tools

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I honestly don't understand that either. I mean, you want to solve something. Then it is in your own interest to provide any and all relevant information to people that might want to help you for free in their own free time for fun.

Why give the shortest possible answer when someone is asking for some clarification. Because while "I use verilog" is sortof an answer to the question, you could be a lot clearer as to what you are doing.

Because we're now at post #10, and that is now slowly starting to look like some useful information. Why not post that information right away?

And yes, that is a serious question.

@gnseeta.btech:
Why don't you post that information right in your first post?

I'm not making fun of you or anything. I really want to know. Is that a cultural thing or something? Only provide information when explicitely asked? From my point of view it seems so counterproductive to getting a solution. But maybe it's what you are used to??

gnseeta.btech said:

i have verilog HDL code with me sir. I have done configuration to spartan3e xc3s1200e board i have got the output on kit. when the same code configured to saprtan3 xc3s400 device i m not getting the output.i have done the recompile( resynthesize, place, route, sta, and bit file generation) with respect to spartan3 board and i have used the ucf file for the xc3s400 board,eventhough i m not getting the output.

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Okay now we are getting somehwere....
So you're trying to port a Verilog HDL BIST design from a 3e to a 3.
Are there any IP cores being used or Coregenerator memories/fifos/dcms etc? If so did you create new ones (retarget) using the correct device information?

Have you gone through the entire compilation log file and verified that the design is in fact getting implemented? How about just checking the resource utilization post map (you'll have to enable that as by default is is disabled) for both the 3e and the 3 versions. The designs should use nearly identical number of resource give or take a few LUTs and registers here and there.

Start with giving us this information and we'll see where it leads.

actually i dnt use any ip cores sir. i have developed verilog HDL code for built in self test(BIST) which is the combination of linear feedback shift register(LFSR),c432 combinational benchmark circuit,multi input signature register(MISR),transition response analyzer(TRA),BIST controller.

i have checked the compilation log file and verified the design on xc3s400 board sir. eventhough i didnt get the output sir....

After telling sparse details about the design purpose, you could probably make a start on explaining what "i didnt get the output" actually means.

In my project i need to detect that whether the circuit under test is faulty or not by glowing the led on the board.i need two led's for 2 outputs.one led for indicating the circuit correctness and the other indicating the test done. i have developed code in such a way that one led should glow for the faultyfree circuit and the other glow after completion of the test(indicating test done).but both the led's are not glowing.

Well I guess the the circuit is faulty and the tests havent completed.