[SOLVED] Dumping out memory addresses and its contents in a file (Xilinx Spartan 6 FPGA)

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dpaul

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Hi all,

I had used Xilinx CoreGen for block RAM generation, then have used the instantiation of it in my design. This RAM is working fine for read and writes - proven in RTL sim.

What I want now is to dump out this particular RAM's addresses and its contents correspondingly as this memory is accessed. This is want to do in the top-level test-bench. The RAM is instantiated somewhere deep down in the design hierarchy.

How can I do this, what are the steps to do this?
Any pointers...

Thanks,
dpaul
 

It would be possible in many ways - but is this Verilog or VHDL?
Would you want to access the actually memory contents, or are you happy to just output the memory d_out as an address is accessed?
The first one would be rather hard, and the 2nd would be quite easy.

More specs?
 

1> Verilog

2> This memory is 1 x 16384 (It can store a single bit, 0 or 1).
Ports - clk, ena (memory enable), wea (erite enable), addra, dina, douta.
Under certain conditions both when ena and wea are HIGH, it is possible to write a single bit into the memory.
It would be sufficient for me to dump/write out to a file the address ("addra") value and the corresponding data being written to it ("dina"). I want to do it in my top-level_test-bench.
Any more info?
 

Use Verilogs . hierarchical reference to the memory array variable. e.g. top.sub.ram.mem_array
You can put that in a for loop and read all the values any time you want from the testbench.
 

ok, I am using $writememb("dump_file.txt", memory_inst) and I get a dump of the memory contents when a particular condition is satisfied. But since in my code, that particular condition is satisfied more than once, so everytime dump_file.txt is being overwritten and I have the last memory contents.
I want the complete dump everytime, APPENDED to a single file, every time when the condition is satisfied. How can I do that?
I know about fwrite(), but cannot figure out how to append the $writememb() value to a file. Is this possible?
 

Open the dump_file.txt with the append option, and don't close it until the simulation finishes. or open (in append mode) and close it each time you need to do $writememb.

I believe that will work, but I haven't tried it. The other option is to do like I previously suggested and just access the memory array directly then you can write all the data in the memory on each satisfied condition in a humanly readable format with $fwrite.
 
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    dpaul

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Thanks ads-ee. Finally I didn't use memory dump methodology. I used file write. My mem generated from Xilinx CoreGen is 1x16384, ie, a memory which can store a single bit and is 16384 deep.

Code Verilog - [expand]
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initial begin : memory_dump_out
    file_name = $fopen("file.txt", "w+");
end
 
always (@ posedge clk) begin
  integer i;
  if (some condition is satisfied) begin
     for (i=0; i<16384; i=i+1) begin
        $fwrite(file_name, "%b \n", top_inst.top_next_inst....<hierarchy comes here>.....blk_mem_gen_v7_3_1x16384_inst.inst.native_mem_module.blk_mem_gen_v7_3_inst.memory[i];
     end
    $fwrite(file_name, "----------------------------");
  end
end
 
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