Dummy transistor and decoupling capacitor

[chang830]

Hi,
We have always add dummy transistors for the devices which need good matching.I wonder how to connect these dummy transistors. Connected the dran, source,bulk,gate together,then tied to VDD? Or Connected the dran, source,bulk,gate together,then tied to GND? Or put them floating? Or connect them as decoupling capacitor?

Always connecting them as decoupling cap have any risks?

I would be happy to hear your advice.

Thanks

 

[vipin_vasudevan]

Hi,

Connectiing dummy mos as decoupling cap may be a little risky ,if it damages the sio2 layer.

 

[scottieman]

I normally connect the dummy to the cleanest ground of my chip in most cases.
Also, the connection should minimize the parasitic to my "actual" transistors. So, in some cases, the dummy is connected to Vdd.

Scottie

 

[chang830]

I normally connect the dummy to the cleanest ground of my chip in most cases.
Also, the connection should minimize the parasitic to my "actual" transistors. So, in some cases, the dummy is connected to Vdd.

Scottie

Hi Scottie,
Thanks for the reply. It is helpful.

Why the dummy connected to Vdd has less parasitic to the "actual" transistors?

Would you elaberate it a bit more?

In many cases I encountered, the dummy Tr are connected as decoupling cap. Except the risks of SiO2 layer damage concern, any other risks do you think?

Thanks

 

[Brittoo]

Hi Chang830

In case of dummy Tx, S,D,B are tied together to the corresponding guard ring. For pfets, it is the N-well tap which is tied to VDD and for Nfets, it is the substrate tap which is connected to Gnd. I believe that answers a part of your initial question.
Connecting the dummiy Tx as decoupling caps also is an alternate option.

Warm regards
Brittoo

 

[hung_wai_ming@hotmail.com]

I noticed that in order to have shared drain/source, the dummies' drain/source should always connect to the working transsitor and the gate should connect to VDD for PMOS and VSS for NMOS. It is better than just place a dummy transistor aside to the real working transistor without sharing source/drain

 

[penchal_gv]

Hi,
In General for dummy Txr, we tied all terminals together and connected to VDD if it is PMOS or it is connected to VSS if it is NMOS.
i didn't how it is acting as decoupling cap because for any CAP require two terminals but here we are tied all together i,e. it is single terminal, plz clarify me.