Puppet123
Full Member level 6
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Hello,
I am doing MMWave IC Layout in (Bi)CMOS processes and am wondering about the effect of metal fill on my passives and interconnect.
Should I EM or schematically simulate the passives and interconnect with a non dummy metal fill and then re simulate again with the dummy metal fill ?
How would I handle this in my design flow - since some or all of the layers in metal fill are automated by the foundry or the PDK.
Thank you.
I am doing MMWave IC Layout in (Bi)CMOS processes and am wondering about the effect of metal fill on my passives and interconnect.
Should I EM or schematically simulate the passives and interconnect with a non dummy metal fill and then re simulate again with the dummy metal fill ?
How would I handle this in my design flow - since some or all of the layers in metal fill are automated by the foundry or the PDK.
Thank you.