Dummy filling in layout design using Assura tool with Cadence

In my experience, two things.

One, foundries nowadays seem to prefer that their CAD folks
add the density fills, while allowing you to place exclusion
polygons where you don't want it. This can make for some
ugly layouts and unexpected couplings. And in this model you
may not be provided the fill-generation script (you could ask).

Two, I prefer to make my own "density fills" which do additional
duty. For example stacked MOS/MOM capacitors will underlie
every bus-rail-pair, and really bump up density in all the involved
layers. In the far field I might place shorted N+/P+ junctions
(w/ active, contact, N+, P+, met1) to act as substrate "getters"
for minority carriers injected. You could lay v1-m6 on top of these
if you want, or leave off if it impacts routing or parasitics. I
prefer fills put where -I- want, rather having (say) fills that
prevent me from inspecting optically or probing into the circuitry
for debug.

Thank you free for your reply,

I have extensively filled the gaps on my design with PSUB contacts. is it good idea?

I understand from you that you also fill beneath your routes, not only adjacent to it, I am afraid it create coupling capacitors.

My DRC rule checker is not complaining about the material density, should I still need to make the filling ?

and how to do it in Assura..
Thanks