Dual well and triple well process

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viperpaki007

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Hi,

Can anybody give pictures of NMOS/PMOS strcutures in dualwell and triple well process. What is the difference between dual well and triple well process.

regards
 

In dual well the NMOS is manufactured on the P-type substrate and for the PMOS an N-Well is created in the substrate where the PMOS is manufactured on this nwell.
In a triple well process, a deep n-well is created in the substrate and in it a p-well is created for the NMOS devices ,in it we have the n-well as before for the PMOS devices.
Here you can connect the bulk of the NMOS device to it source without it being grounded (e.g. cascode structure) , thus removing the body effect (but adding extra parasitic capacitance from the bulk diode) and improving the noise isolation.
 

viperpaki007 said:
Can anybody give pictures of NMOS/PMOS strcutures in dualwell and triple well process. What is the difference between dual well and triple well process.
Click to expand...

Didn't you ask this very same question in April last year? See Similar Threads below!
 
Hi erik,

One question still remains unclear. As far as i have understood, dual well process is used to isolate NMOS and PMOS from substrate. If dual well can do this isolation then why there is a need for triple well process.
 

beeflobill is right: the third nwell, usually called deep nwell or high-voltage (HV)nwell, deeper and more lightly (even retrograde) doped than the normal LVnwell is used for so-called lowly doped (LD) HV devices:


Another use for the 3rd nwell is for creating very well ;-) β-controlled vertical bipolar NPN transistors:
 
 

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