Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Dual charge pump PLL oscilating

Status
Not open for further replies.

sainiparvesh

Newbie level 6
Newbie level 6
Joined
Jul 1, 2009
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
noida
Activity points
1,371
Hi,
I am converting a single charge pump PLL having loop element as R, Cbig, Csmall and CP current as Icp, into dual charge pump PLL having loop element R(=1/gm, unity gain buffer o/p impedence), Cbig/2, Csmall/2 and proportional and integral charge pump current as Icp and Icp/2. As per MATLAB simulations it gives aprox. same phase margin and bandwidth but real implementation gives oscillations in control voltage and o/p freq. while origional PLL is having ~50degree PM. Is there any other parameter needs to be changed to reduce loop cap(Cbig) by 2. I have implemented R using unity gain buffer after Cbig.
 

implementation gives oscillations in control voltage and o/p freq. while origional PLL is having ~50degree PM.

1.

I suppose you wish to eliminate the unwanted oscillations?

These are likely to happen when resistor values are low, allowing excessive current flow. That is, if the components will provide it.

If they won't allow it, then it may pull down volt levels on certain components.

In turn this changes some other behavior, which the oscillator tries to compensate for, etc...

The result is unwanted oscillations.

2.

The large phase modulation (I think that is what you mean by PM) occurs on a capacitor in combination with a low resistance.

To solve these problems, it might help to increase some or all resistor values, and reduce capacitor values. It is possible to do this while maintaining a desired frequency of oscillation.
 

Hello Brad,
Thanks for your suggestions, it is quite informative for me and further add into my knowledge about CPPLL. Actually I solved this problem. There was the issue with big loop cap, there was a connection problem due to which actual big loop cap was not coming into picture and loop was oscillating. Anyway by PM I mean phase margin.

Thanks for your nice explanation once again.

Regards,
Pravesh

1.

I suppose you wish to eliminate the unwanted oscillations?

These are likely to happen when resistor values are low, allowing excessive current flow. That is, if the components will provide it.

If they won't allow it, then it may pull down volt levels on certain components.

In turn this changes some other behavior, which the oscillator tries to compensate for, etc...

The result is unwanted oscillations.

2.

The large phase modulation (I think that is what you mean by PM) occurs on a capacitor in combination with a low resistance.

To solve these problems, it might help to increase some or all resistor values, and reduce capacitor values. It is possible to do this while maintaining a desired frequency of oscillation.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top