Hi,
I worked with someone whio said Dual cascaded boost should always be done cheaply with no comparator current sense on the 2nd transistor...and just make it an IGBT, in case an overcurrent ever flows through it, it will be more likely to survive it if its an IGBT.......so this was a good way to save money and avoid 2 current sense comparators.
Would you agree its a cheaper way?
Or would you say at 100kHz, tail current issues would dictate against this.?
Also, isnt it a strange thing (?question?) about the cascaded booster, that even if the upstream inductor is in deep CCM, the downstream inductor can be in deep DCM , and it all still works perfectly well....just the mid_level voltage is slightly lower than would be than if both were in CCM.
The mid level rail also never approachs the actual output in voltage, even though the mid-level rail is effectively unregulated.....so why is the cascaded booster not more popular?
Thanks, i will seek further papers.
The first time i met the "cascader" was the cascaded buck.....where i worked on a 400v to 100v cascaded buck for 300w....(it was a re-hash of a PCB for 400V to 12v buck) for downhole use.....it worked well, and literally had no "extra" components that you might expect for a converter that was basically giving you "2 bucks for the price of one" so to speak. The middle rail is essentially unregulated, but behaved very well....no current limiting on the downstream fet but no problem. No overvoltage on the upstream fet, even though its output is essentially unregulated.
Very surprised not to hear more papers on it though...as when compared to 2 consecutive boosters......you get hit with dualling feedback loops, the need for higher "middle rail" capacitance, and the need for higher inductance of the downstream one, and the obvious need for 2 control chips. So the lack of papers surprises me.
Must admit, many of the papers seem a bit, "not in depth"
This Paper proposes a high voltage gain dc-dc lift-up converter for photovoltaic based power generation especially used for microgrid applications. Pr…
This paper deals with a new approach to obtain a boost dc-dc converter with a very high voltage boost rate (e.g., 8 in practice or 16 in theoretical study) and a high efficiency by means of two single-ended boost dc-dc converters connected in cascade. A part of the whole study, i.e., the...
There are papers on cascaded booster with coupled inductors....cant think why on earth anyone would want the bother of coupled inductors for this.
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In the attached cascaded booster ltspice sim i managed to "hack" it so the mid rail goes up to 68vpk....normal is 58v...but cant get it any higher than 68v.....you just cant break the thing......why is a paper even needed for it?...its just literally 2 boosters "joined at the hip"
I googled "problems with cascaded boost converter" and get nothing.
Thinking about putting overvoltage protection on the mid rail, and overcurrent protection on the downstream fet...but its impossible to really say that these protections will ever be called into action.
Given that boosters have diodes to the output - no real current limit is possible, you can of course limit the pk curr in each fet - which is usually a prudent thing to do.
Running the same D in each fet, it is a good idea to have the same % ripple in each choke, and the same proportionality of Cout for each stage - this will help in a lot of ways.
Thanks, for us cost has meant that the percentage ripple in the downstream inductor is significantly more than in the upstream inductor. If we wanted same ripple percentage, (which is indeed what we were aiming for initially) it woudl have meant higher downstream inductance, and it couldnt be done as cheaply.
BTW, we opted for 8 boosters in parallel in the end, and got the above inductor a bit smaller.
It was found that a torroid with high permeability was needed for the upstream inductor, (so low number of tunrs as high current) and with low permeability for the downstream inductor...as lowering the core loss prooved cheaper.