Although at first glance this should work, surely doing a logical inversion by an algebraic operation is not the usual way of toggling a bit. Consider instead of doing a toogle, just forcing to a fixed value, .
Although at first glance this should work, surely doing a logical inversion by an algebraic operation is not the usual way of toggling a bit. Consider instead of doing a toogle, just forcing to a fixed value, .
I also changed the void main() to int main() with a return 0; still no show.
I still wonder if there is a register or something else I need to set. The uniformity of interval of the restart is exact, Meaning something internal or by default is resetting.
I'm not that familiar with dsPIC30 series code but a restart at fixed intervals regardless of the coding strongly suggests a watchdog issue. I assume the line "_FWDT(WDT_OFF);" turns it off, is there another control for the watchdog, maybe in the device config that needs attention?
I'm not that familiar with dsPIC30 series code but a restart at fixed intervals regardless of the coding strongly suggests a watchdog issue. I assume the line "_FWDT(WDT_OFF);" turns it off, is there another control for the watchdog, maybe in the device config that needs attention?
Since I don't have any readout attached yet to the dsPIC30F, I was able to use LED pattern to confirm the cause of reset via the WDTO bit of RCON. Please, is there anyway RCONbits check can be integrated in code to resolve issues automatically besides development test?
Thanks,
I tried the new config as below with no success. The reset was ongoing unless I use CLRWDT. I believe the chip is bad. I will be receiving new dsPIC from my supplier soon to confirm if it is chip level failure.
The prescaler A and B setting explains the >10seconds reset interval I was getting. Strange indeed! Let's assume it is chip partial failure.
I am running at 6MHz and PLL_16 which should be 24 MIPS Tcy = 41.6ns. That means 1 sec delay should be __delay32(24000000) but __delay32(2400000) was the correct value on the physical chip against my math.
The answer, as so often happens, is in the data sheet. The last paragraph of Section 19.4.2 says that, if you turn off the config bit, then the WDT is controlled by software with the SWDTEN bit. Make sure this is bit is 0.
Susan
The answer, as so often happens, is in the data sheet. The last paragraph of Section 19.4.2 says that, if you turn off the config bit, then the WDT is controlled by software with the SWDTEN bit. Make sure this is bit is 0.
Susan
I believe clearing the entire RCON bits does the job of ensuring SWDTEN = 0.
Update will be made when I receive new dsPIC chips, as I have agreed my dsPIC chip is faulty. It will be interesting to find out.