Hi, I am familiar with using dual port Block RAMs in Xilinx FPGAs. We usually generate the Block RAM IP Core in Xilinx Vivado and configure their ports, size and memory width etc. Then we instantiate the digital design to perform read/write operations between the digital design and the Block RAMs.
How do we work with DSP slices ? and do we also need to intentionally add in our design ? Do we also configure each DSP slice we need to add in our design and in what application we need to use DSP slices ?