Two possibilities, same chip, one chip, ARM + 2 SARs + 1 DelSig + Vref + see below
First top example using the Delsig, it can do 48KSPS @ 16 bits, uses on chip T & H to
enforce simul sampling. Note its effective rate is 24 KSPS which means you would skip
/ ignore every other incoming sample (cycle to cycle basis) to get your target speed.
If your design needs cannot work missing every other incoming sample this would
not be adequate.
The bottom example, 2 SARs (onchip) is 12 bits, but one could use averaging of
samples to get to 16 bits as it can convert at, in this config, 666KSPS. The Start of
Conversion input to SAR you can hook to whatever you want to trigger the simul-
taneous sampling of the 2 SARs. Ap notes on averaging and ENOB improvement
attached.
This is overall whats on the chip, multiple copies in many cases, like 4 OpAmps,
4 DACs, lots of logic elements, the M3 ARM core.........
Regards, Dana.