We are using DS90UB960-Q1 n our design. The layout guideline(Page no 178) says ". Minimize intra-pair and inter-pair length mismatch within a single CSI-2 TX Port (recommended <= 5 mils)."
Our layout team is not able to achieve this. The best they can achieve is 250mils.
Don't know how they arrive at 5 mils mismatch. MIPI spec specificies maximal delay skew between clock and data of 1/50 UI, which is 12.5 ps at 1.6 GBPS. Corresponds to about 75 mils with usual FR-4 propagation speed. 250 mils is definitely beyond limits.
This is very informative.
I think TI have some confusion in this. Below is the guidance they provided in the reference design.
Here it is 10mils and in datasheet it is 5mils.
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I tried to back calculate how you arrived 75mils.Please let me know it is fine or not.
Show your layout and PCB design rules, laminate materials. You must meet the specs.
You will be disappointed with std FR4.
I'd recommend Getek ML200C Er= 3.8 Tpd =5.42 ps/mm
Yes.
The 1/50 UI skew limit has to be shared by the total transmission path, TX, RX PCB and cable. 75 mil describes the case where RX and TX are on the same PCB.