driving test pattern into memory of a synthesized MIPS netlist

I am simulating a mips verilog netlist from my testbench. ROM memory block is modelled as a wire in the netlist although its connected to D flops.

module instruction_mem(clk, pc, instruction);
input clk;
input [7:0] pc;
output [15:0] instruction;
wire clk;
wire [7:0] pc;
wire [15:0] instruction;
wire [15:0] \rom[195] ;*
wire [15:0] \rom[67] ;
wire [15:0] \rom[146] ;
wire [15:0] \rom[19] ;
I tried driving testpatterns to the memory blocks by using readmemb/fscanf(just like what I did in RTL).It failed. From the link here, i learnt i couldnt use any of such fileI/O functions during netlist-simulation.

So i am trying to drive these signals through instantiation.

mips_16_core_top uut (
.clk(clk),
.rst(rst),
.pc(pc)
.IF_stage_inst.imem.\rom[67] (16'b1001001000011100)
.IF_stage_inst.imem.\rom[67] (1'b0)
);
What is the syntax to instantiate sub-lower modules in a testbench? For eg in the above case, its like this:

mips_16_core_top
-->IF_stage.v
-> instruction_mem.v => rom memory.
But in my netlist,rom has been modelled as a wire with connections to D flip-flops. Simply put, how do i simulate memory blocks at a gate level? Also how do i drive heirarchicaly-lower level nets/registers during instantiation?

you could force the output of the flop with the value you have on the ROM code.
Personnaly, to avoid manipulate "\" caracter, which it is not "easy" in TCL, I configure the synthesis tool to not be allowed to used this caracter, and also "[", "]".
In verilog a name starting with "\" include a space caracter at the end to finish the name.

You could recompile only the sub-module rom used in RTL, if the pins I/O is the same with your netlist, but the timing back-annotated could be lost.