DRC Error: N+SD Iso Psub tap spacing must be <=10.0 um

[sp.bhuvana]

Hi, Iam new to Virtuoso Layout L. I tried to simulate LNA using nmoscap from gpdk180. Iam getting an DRC error stating that "N+SD Iso Psub tap spacing must be <=10.0 um". Kindly help me to clear that error

 

[rangermad]

Sounds like you need to add a psub tap next to your N+SD.

 

[sp.bhuvana]

Sounds like you need to add a psub tap next to your N+SD.

I have already attached Psub tap to N+SD... Still same error exists... And also tried by attaching IsoPwell tap... still getting same error... Kindly help me...

 

[erikl]

I have already attached Psub tap to N+SD... Still same error exists...

Did you connect the Psub via a contact to M1 to GND? If not, it doesn't work. If yes, you better provide an image of the field of your problem.

 

[dick_freebird]

If the cap is any useful size you probably need more
than "a" Ptap. Why can you not see by the displayed
error marker, where the device check is unhappy?

 

[sp.bhuvana]

Did you connect the Psub via a contact to M1 to GND? If not, it doesn't work. If yes, you better provide an image of the field of your problem.

Hi Erikl,
Sorry for the delayed reply. Herewith i have attached the image of my problem.

 

[erikl]

Not sure if I interpret your colors correctly. At the left side to me it seems you have an Nimplant within a Pimplant crossing the Nwell border (connected to the D? of the nmos, pls. see the picture below), which isn't a valid Ptap.

​

At the right side it seems there is one more Pimplant partly within the Nwell (connected to the S?), which isn't a valid Ptap as well.

Valid Ptaps should have a P+diff on psub outside - but not too far (<=10µm , in your case) from - the Nwell border, and then be connected through a contact to ME1 and to GND - not to the Source, and generally also not to the Drain of the Nmos.

 

[sp.bhuvana]

Not sure if I interpret your colors correctly. At the left side to me it seems you have an Nimplant within a Pimplant crossing the Nwell border (connected to the D? of the nmos, pls. see the picture below), which isn't a valid Ptap.

View attachment 151929​

At the right side it seems there is one more Pimplant partly within the Nwell (connected to the S?), which isn't a valid Ptap as well.

Valid Ptaps should have a P+diff on psub outside - but not too far (<=10µm , in your case) from - the Nwell border, and then be connected through a contact to ME1 and to GND - not to the Source, and generally also not to the Drain of the Nmos.

Hi Erikl,
Actually to the left of NMOS is Nwell Tap(Nwell with Nimp). If i do not connect the Nwell tap, iam getting the DRC error stating that "NBuried Stamp_error Float" as shown in the picture.
And Also as u said, i have connected Psub tap nearer to Nwell, still same error exists... What should i do?