mursina
Newbie
These are some DRC error I am getting when I try to check DRC with IO pads, without IO pads these errors are not coming.
I kept p+ and n+ guardning also, but still these errors are not going, can someone please tell how to resolve this, thanks in advance 1. LUP.2g { @ Within 15 um space from the OD injector, a P+ guard-ring is required to surround an NMOS or an NMOS cluster. And an N+ guard-ring is required to surround a PMOS or a PMOS cluster.
2. LUP.5.1.1g {@ Minimum space >= 2 um
@ 1. between 1.2V-1.0V N+ OD injector which connects to the IO pad and the the PMOS in the internal circuit
@ 2. between 1.2V-1.0V P+ OD injector which connects to the IO pad and the the NMOS in the internal circuit
3. LUP.5.1.2g {@ Minimum space >= 3 um if one of guard-ring < 0.2 um
@ 1. between 1.2V-1.0V N+ OD injector which connects to the IO pad and the the PMOS in the internal circuit
@ 2. between 1.2V-1.0V P+ OD injector which connects to the IO pad and the the NMOS in the internal circuit
4. LUP.1g { @ Any N+ OD injector or an N+ OD injector cluster connected to an I/O pad must be surrounded by a P+ guard-ring.
@ Any P+ OD injector or a P+ OD injector cluster connected to an I/O pad must be surrounded by a N+ guard-ring.
I kept p+ and n+ guardning also, but still these errors are not going, can someone please tell how to resolve this, thanks in advance 1. LUP.2g { @ Within 15 um space from the OD injector, a P+ guard-ring is required to surround an NMOS or an NMOS cluster. And an N+ guard-ring is required to surround a PMOS or a PMOS cluster.
Code:
X = BESIDE_POST_DRIVER_NMOS_RW INTERACT (DNW INTERACT ((NWEL INTERACT (DNW INTERACT BESIDE_POST_DRIVER_NMOS_RW)) INTERACT POST_DRIVER_PMOS_NW))
Y = EXT POST_DRIVER_PMOS_NWi [BESIDE_POST_DRIVER_NMOS_RWi] < LUP_2 ABUT < 90 SINGULAR NOT CONNECTED
BESIDE_POST_DRIVER_NMOS_waive = (BESIDE_POST_DRIVER_NMOS_RWi NOT INTERACT X) NOT WITH EDGE Y
(BESIDE_POST_DRIVER_NMOS NOT BESIDE_POST_DRIVER_NMOS_waive) NOT INSIDE PTAP_guard_ring_hole
BESIDE_POST_DRIVER_PMOS NOT INSIDE NTAP_guard_ring_hole
}2. LUP.5.1.1g {@ Minimum space >= 2 um
@ 1. between 1.2V-1.0V N+ OD injector which connects to the IO pad and the the PMOS in the internal circuit
@ 2. between 1.2V-1.0V P+ OD injector which connects to the IO pad and the the NMOS in the internal circuit
Code:
EXT POST_DRIVER_PINJ_NW_LV BESIDE_POST_DRIVER_NMOS_PW < LUP_5_1_1 ABUT < 90 SINGULAR //REGION
EXT POST_DRIVER_PINJ_NW_LV BESIDE_POST_DRIVER_NMOS_RW < LUP_5_1_1 ABUT < 90 SINGULAR CONNECTED //REGION
EXT POST_DRIVER_PINJ_NWi_LV BESIDE_POST_DRIVER_NMOS_RWi < LUP_5_1_1 ABUT < 90 SINGULAR NOT CONNECTED //REGION
EXT POST_DRIVER_NINJ_PW_LV BESIDE_POST_DRIVER_PMOS_NW < LUP_5_1_1 ABUT < 90 SINGULAR //REGION
EXT POST_DRIVER_NINJ_RW_LV BESIDE_POST_DRIVER_PMOS_NW < LUP_5_1_1 ABUT < 90 SINGULAR CONNECTED //REGION
EXT POST_DRIVER_NINJ_RWi_LV BESIDE_POST_DRIVER_PMOS_NWi < LUP_5_1_1 ABUT < 90 SINGULAR NOT CONNECTED //REGION
}3. LUP.5.1.2g {@ Minimum space >= 3 um if one of guard-ring < 0.2 um
@ 1. between 1.2V-1.0V N+ OD injector which connects to the IO pad and the the PMOS in the internal circuit
@ 2. between 1.2V-1.0V P+ OD injector which connects to the IO pad and the the NMOS in the internal circuit
Code:
EXT POST_DRIVER_PINJ_NW_LV_NG BESIDE_POST_DRIVER_NMOS_PW < LUP_5_1_2 ABUT < 90 SINGULAR //REGION
EXT POST_DRIVER_PINJ_NW_LV_NG BESIDE_POST_DRIVER_NMOS_RW < LUP_5_1_2 ABUT < 90 SINGULAR CONNECTED //REGION
EXT POST_DRIVER_PINJ_NWi_LV_NG BESIDE_POST_DRIVER_NMOS_RWi < LUP_5_1_2 ABUT < 90 SINGULAR NOT CONNECTED //REGION
EXT POST_DRIVER_NINJ_PW_LV_NG BESIDE_POST_DRIVER_PMOS_NW < LUP_5_1_2 ABUT < 90 SINGULAR //REGION
EXT POST_DRIVER_NINJ_RW_LV_NG BESIDE_POST_DRIVER_PMOS_NW < LUP_5_1_2 ABUT < 90 SINGULAR CONNECTED //REGION
EXT POST_DRIVER_NINJ_RWi_LV_NG BESIDE_POST_DRIVER_PMOS_NWi < LUP_5_1_2 ABUT < 90 SINGULAR NOT CONNECTED //REGION
EXT POST_DRIVER_PINJ_NW_LV BESIDE_POST_DRIVER_NMOS_PW_NG < LUP_5_1_2 ABUT < 90 SINGULAR //REGION
EXT POST_DRIVER_PINJ_NW_LV BESIDE_POST_DRIVER_NMOS_RW_NG < LUP_5_1_2 ABUT < 90 SINGULAR CONNECTED //REGION
EXT POST_DRIVER_PINJ_NWi_LV BESIDE_POST_DRIVER_NMOS_RWi_NG < LUP_5_1_2 ABUT < 90 SINGULAR NOT CONNECTED //REGION
EXT POST_DRIVER_NINJ_PW_LV BESIDE_POST_DRIVER_PMOS_NW_NG < LUP_5_1_2 ABUT < 90 SINGULAR //REGION
EXT POST_DRIVER_NINJ_RW_LV BESIDE_POST_DRIVER_PMOS_NW_NG < LUP_5_1_2 ABUT < 90 SINGULAR CONNECTED //REGION
EXT POST_DRIVER_NINJ_RWi_LV BESIDE_POST_DRIVER_PMOS_NWi_NG < LUP_5_1_2 ABUT < 90 SINGULAR NOT CONNECTED //REGION
}4. LUP.1g { @ Any N+ OD injector or an N+ OD injector cluster connected to an I/O pad must be surrounded by a P+ guard-ring.
@ Any P+ OD injector or a P+ OD injector cluster connected to an I/O pad must be surrounded by a N+ guard-ring.
Code:
POST_DRIVER_NACT NOT INSIDE PTAP_guard_ring_hole
POST_DRIVER_PACT NOT INSIDE NTAP_guard_ring_hole
}
Last edited by a moderator: