DRC error in tsmc 65nm with io pads

[mursina]

Hello, I already kept guard ring around the most but still this LUP. 2g error is coming, also I have checked tsmc 65nm guideline PDF there they wrote
(Within 15um space from the OD injector, a P+ guard-ring is required to

surround an NMOS or an NMOS cluster. And an N+ guard-ring is
required to surround a PMOS or a PMOS cluster.
NMOS guard-ring are exempt from the following conditions.
If the NMOS is enclosed by a DNW, the NW of the checked PMOS does
not interact with the DNW, and the voltage (Va) of the NW INTERACT
DNW is ≥ the voltage (Vb) of the NW of the checked PMOS.)

DRC error :
LUP.2g { @ Within 15 um space from the OD injector, a P+ guard-ring is required to surround an NMOS or an NMOS cluster. And an N+ guard-ring is required to surround a PMOS or a PMOS cluster.
X = BESIDE_POST_DRIVER_NMOS_RW INTERACT (DNW INTERACT ((NWEL INTERACT (DNW INTERACT BESIDE_POST_DRIVER_NMOS_RW)) INTERACT POST_DRIVER_PMOS_NW))
Y = EXT POST_DRIVER_PMOS_NWi [BESIDE_POST_DRIVER_NMOS_RWi] < LUP_2 ABUT < 90 SINGULAR NOT CONNECTED
BESIDE_POST_DRIVER_NMOS_waive = (BESIDE_POST_DRIVER_NMOS_RWi NOT INTERACT X) NOT WITH EDGE Y
(BESIDE_POST_DRIVER_NMOS NOT BESIDE_POST_DRIVER_NMOS_waive) NOT INSIDE PTAP_guard_ring_hole
BESIDE_POST_DRIVER_PMOS NOT INSIDE NTAP_guard_ring_hole
}


Can someone please tell how to resolve this?

--- Updated Jun 20, 2024 ---

I already kept guard ring around Mos, but still I am getting LUP. 2g DRC error, can someone please tell how to resolve this?


DRC error :
LUP.2g { @ Within 15 um space from the OD injector, a P+ guard-ring is required to surround an NMOS or an NMOS cluster. And an N+ guard-ring is required to surround a PMOS or a PMOS cluster.
X = BESIDE_POST_DRIVER_NMOS_RW INTERACT (DNW INTERACT ((NWEL INTERACT (DNW INTERACT BESIDE_POST_DRIVER_NMOS_RW)) INTERACT POST_DRIVER_PMOS_NW))
Y = EXT POST_DRIVER_PMOS_NWi [BESIDE_POST_DRIVER_NMOS_RWi] < LUP_2 ABUT < 90 SINGULAR NOT CONNECTED
BESIDE_POST_DRIVER_NMOS_waive = (BESIDE_POST_DRIVER_NMOS_RWi NOT INTERACT X) NOT WITH EDGE Y
(BESIDE_POST_DRIVER_NMOS NOT BESIDE_POST_DRIVER_NMOS_waive) NOT INSIDE PTAP_guard_ring_hole
BESIDE_POST_DRIVER_PMOS NOT INSIDE NTAP_guard_ring_hole
}

 

[aliarifat794]

Hello, sorry you did not mention which software you're using. You did not share any screenshot. I think screenshot will be good. It will help experts here to find the exact problem. However, for more info about the PCB design rule check, you can see here: https://www.pcbway.com/pcb_prototype/PCB_Design_Rule_Check.html