It's possible that there is some rules logic that looks for pad-cut
(silox, whatever) and then enables I/O and antenna rules for
chip level signoff completeness. You could read the rules deck
and dope that out. The rule looks like an antenna rule, which I
am seeing a distinct rules-set for in my current foundry. Maybe
yours has an all-in-one, but modal based on content, setup.
Look to the detailed result, which should highlight a net (or nets)
which offend. Measure the metal area and the gate area and
satisfy yourself that the rules logic is being triggered. If so then
consider the usual antenna strategies - breaking and via-jumper-
re-connecting the metal trace, using an antenna diode to fix it,
whatever your options may be. I'd recommend searching through
the foundry PDK docs for "antenna" to see what they have for
you, in this vein.