ktx2222
Member level 5
![Member level 5](/styles/images/ranks/dlevel5.gif)
Hi,
I have an error of DRC (calibre DRC, ibm CMRF7SF pdk, Cadence IC615):
GR131_top: All (Gates not over TG) must meet the ratio of AM metal area to {(PC over RX oxide area) + 10 x (diode diffusion area)} <=150.
- I created a core layout. I pass DRC of core layout.
- I added the I/O Pads and the error occured.
- I removed the connection of AM metal to the core circuit, but error still happened.
![2015-04-26 1-06-21 PM.png 2015-04-26 1-06-21 PM.png](https://www.edaboard.com/data/attachments/52/52539-7552b61be12216ca23e7308ff4a5e841.jpg)
Does anyone have experience about this? Please help.
I have an error of DRC (calibre DRC, ibm CMRF7SF pdk, Cadence IC615):
GR131_top: All (Gates not over TG) must meet the ratio of AM metal area to {(PC over RX oxide area) + 10 x (diode diffusion area)} <=150.
- I created a core layout. I pass DRC of core layout.
- I added the I/O Pads and the error occured.
- I removed the connection of AM metal to the core circuit, but error still happened.
![2015-04-26 1-06-21 PM.png 2015-04-26 1-06-21 PM.png](https://www.edaboard.com/data/attachments/52/52539-7552b61be12216ca23e7308ff4a5e841.jpg)
Does anyone have experience about this? Please help.