vaah
Member level 3
Hello all,
I am layouting a block using TSMC65nm. I got a DRC error which I don't know how to clean it. I was wondering if anyone has faced this error and knows how to clean it.
Thank you.
error:
width > 0.3 um (W). (It is allowed to use one VIAx for a connection that is > 0.8 um (D) away from a metal plate (either Mx or Mx+1) with length > 0.3 um (L) and width > 0.3 um (W).)
Branch1 = ((SIZE M3Wide_0.7_VIA2 BY VIA2_R_4_D + GRID) NOT M3Wide_0.7_VIA2) AND M3
Branch1HasVia = (Branch1 INTERACT M3Wide_0.7_VIA2) INTERACT VIA2
Branch1Edge = M3Wide_0.7_VIA2 COIN OUTSIDE EDGE Branch1HasVia
Branch1Rec = EXPAND EDGE Branch1Edge OUTSIDE BY GRID
Branch = SIZE Branch1Rec BY VIA2_R_4_D INSIDE OF Branch1HasVia STEP M3_S_1*0.5
GoodBranch = (Branch AND M2) INTERACT VIA2 > 1
BranchSingleVia = (VIA2 NOT OUTSIDE Branch) OUTSIDE GoodBranch
Bad_Region = (((M2 INTERACT BranchSingleVia) AND M3) INTERACT BranchSingleVia) INTERACT VIA2 == 1
(BranchSingleVia INTERACT Bad_Region) NOT VIA_EXD
I am layouting a block using TSMC65nm. I got a DRC error which I don't know how to clean it. I was wondering if anyone has faced this error and knows how to clean it.
Thank you.
error:
width > 0.3 um (W). (It is allowed to use one VIAx for a connection that is > 0.8 um (D) away from a metal plate (either Mx or Mx+1) with length > 0.3 um (L) and width > 0.3 um (W).)
Branch1 = ((SIZE M3Wide_0.7_VIA2 BY VIA2_R_4_D + GRID) NOT M3Wide_0.7_VIA2) AND M3
Branch1HasVia = (Branch1 INTERACT M3Wide_0.7_VIA2) INTERACT VIA2
Branch1Edge = M3Wide_0.7_VIA2 COIN OUTSIDE EDGE Branch1HasVia
Branch1Rec = EXPAND EDGE Branch1Edge OUTSIDE BY GRID
Branch = SIZE Branch1Rec BY VIA2_R_4_D INSIDE OF Branch1HasVia STEP M3_S_1*0.5
GoodBranch = (Branch AND M2) INTERACT VIA2 > 1
BranchSingleVia = (VIA2 NOT OUTSIDE Branch) OUTSIDE GoodBranch
Bad_Region = (((M2 INTERACT BranchSingleVia) AND M3) INTERACT BranchSingleVia) INTERACT VIA2 == 1
(BranchSingleVia INTERACT Bad_Region) NOT VIA_EXD